yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 18:15:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: Fix aarch64 vec_reg_offset

Browse source 
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended. Fix this by adding
in the vfp.regs offset after computing the inter-register offset.

Backports commit d437262fa8edd0d9fbe038a515dda3dbf7c5bb54 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 09:35:59 -05:00 committed by Lioncash
parent ce9dca9c5e
commit 0f94929fa7
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
qemu/target-arm/translate-a64.c
View file

@ -554,7 +554,7 @@ static inline void assert_fp_access_checked(DisasContext *s)
static inline int vec_reg_offset(DisasContext *s, int regno, static inline int vec_reg_offset(DisasContext *s, int regno,
int element, TCGMemOp size) int element, TCGMemOp size)
{ {
int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); int offs = 0;
#ifdef HOST_WORDS_BIGENDIAN #ifdef HOST_WORDS_BIGENDIAN
/* This is complicated slightly because vfp.regs[2n] is /* This is complicated slightly because vfp.regs[2n] is
* still the low half and vfp.regs[2n+1] the high half * still the low half and vfp.regs[2n+1] the high half
@ -567,6 +567,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
#else #else
offs += element * (1 << size); offs += element * (1 << size);
#endif #endif
offs += offsetof(CPUARMState, vfp.regs[regno * 2]);
assert_fp_access_checked(s); assert_fp_access_checked(s);
return offs; return offs;
} }