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target/riscv: fix vector index load/store constraints

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Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.

And this constraint has been added to the v0.8 spec.

Backports 3e09396e36dff4234afd6f6fd51861949be383e1
This commit is contained in:
LIU Zhiwei 2021-03-08 12:16:43 -05:00 committed by Lioncash
parent fdfa52f424
commit 0f95c05ca4
1 changed files with 9 additions and 1 deletions
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10
qemu/target/riscv/insn_trans/trans_rvv.inc.c
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@ -520,13 +520,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
/*
* For vector indexed segment loads, the destination vector register
* groups cannot overlap the source vector register group (specified by
* `vs2`), else an illegal instruction exception is raised.
*/
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
vext_check_nf(s, a->nf));
vext_check_nf(s, a->nf) &&
((a->nf == 1) ||
vext_check_overlap_group(a->rd, a->nf << s->lmul,
a->rs2, 1 << s->lmul)));
}
GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)