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target/mips: Mark switch fallthroughs with interpretable comments

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Mark switch fallthroughs with comments, in cases fallthroughs
are intentional.

The comments "/* fall through */" are interpreted by compilers and
other tools, and they will not issue warnings in such cases. For gcc,
the warning is turnend on by -Wimplicit-fallthrough. With this patch,
there will be no such warnings in target/mips directory. If such
warning appears in future, it should be checked if it is intentional,
and, if yes, marked with a comment similar to those from this patch.

The comment must be just before next "case", otherwise gcc won't
understand it.

Backports commit 146dd620db815558938433eb9f57a571d424d2c6 from qemu
This commit is contained in:
Aleksandar Markovic 2018-08-17 14:17:37 -04:00 committed by Lioncash
parent 0f118a005b
commit 0fd3ae0efb
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 2 deletions
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5
qemu/target/mips/translate.c
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@ -14410,8 +14410,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case SDP: case SDP:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
/* Fallthrough */
#endif #endif
/* fall through */
case LWP: case LWP:
case SWP: case SWP:
gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@ -14421,8 +14421,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case SDM: case SDM:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
/* Fallthrough */
#endif #endif
/* fall through */
case LWM32: case LWM32:
case SWM32: case SWM32:
gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@ -20259,6 +20259,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
case OPC_MTHC1: case OPC_MTHC1:
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
/* fall through */
case OPC_MFC1: case OPC_MFC1:
case OPC_CFC1: case OPC_CFC1:
case OPC_MTC1: case OPC_MTC1: