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target/riscv: Correctly implement TSR trap
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu
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@ -84,7 +84,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
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}
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if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
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get_field(env->mstatus, MSTATUS_TSR)) {
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get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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