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target/riscv: Convert RV64I load/store insns to decodetree

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this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.

Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-18 16:02:12 -04:00 committed by Lioncash
parent 65a415372b
commit 1024ceb4df
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 25 additions and 10 deletions
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8
qemu/target/riscv/Makefile.objs
View file

@ -3,10 +3,12 @@ obj-y += unicorn.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/riscv/decode_insn32.inc.c: \
$(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE)
decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
"GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c

20
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -132,3 +132,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
return true;
}
#ifdef TARGET_RISCV64
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm);
return true;
}
static bool trans_ld(DisasContext *ctx, arg_ld *a)
{
gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm);
return true;
}
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
return true;
}
#endif

7
qemu/target/riscv/translate.c
View file

@ -1981,13 +1981,6 @@ static void decode_RV32_64G(DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
case OPC_RISC_LOAD:
gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
break;
case OPC_RISC_STORE:
gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2,
GET_STORE_IMM(ctx->opcode));
break;
case OPC_RISC_ARITH_IMM:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_IMM_W: