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target/mips: Fix block-comment-related issues in msa_helper.c

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Fix block-comment-related issues reported by checkpatch for file
msa_helper.c.

Backports commit 7cc8a7220de39d77894edcb376378f280ec9c4c2 from qemu
This commit is contained in:
Aleksandar Markovic 2019-06-10 13:53:43 -04:00 committed by Lioncash
parent b9d8008931
commit 10b0f86caf
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 27 additions and 15 deletions
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42
qemu/target/mips/msa_helper.c
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@ -1974,8 +1974,10 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
c &= ~FP_UNDERFLOW;
}
/* Reciprocal operations set only Inexact when valid and not
divide by zero */
/*
* Reciprocal operations set only Inexact when valid and not
* divide by zero
*/
if ((action & RECIPROCAL_INEXACT) &&
(c & (FP_INVALID | FP_DIV0)) == 0) {
c = FP_INEXACT;
@ -1984,15 +1986,19 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
cause = c & enable; /* all current enabled exceptions */
if (cause == 0) {
/* No enabled exception, update the MSACSR Cause
with all current exceptions */
/*
* No enabled exception, update the MSACSR Cause
* with all current exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
(GET_FP_CAUSE(env->active_tc.msacsr) | c));
} else {
/* Current exceptions are enabled */
if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
/* Exception(s) will trap, update MSACSR Cause
with all enabled exceptions */
/*
* Exception(s) will trap, update MSACSR Cause
* with all enabled exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
(GET_FP_CAUSE(env->active_tc.msacsr) | c));
}
@ -3056,9 +3062,11 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
/* Half precision floats come in two formats: standard
IEEE and "ARM" format. The latter gains extra exponent
range by omitting the NaN/Inf encodings. */
/*
* Half precision floats come in two formats: standard
* IEEE and "ARM" format. The latter gains extra exponent
* range by omitting the NaN/Inf encodings.
*/
flag ieee = 1;
MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
@ -3614,9 +3622,11 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
/* Half precision floats come in two formats: standard
IEEE and "ARM" format. The latter gains extra exponent
range by omitting the NaN/Inf encodings. */
/*
* Half precision floats come in two formats: standard
* IEEE and "ARM" format. The latter gains extra exponent
* range by omitting the NaN/Inf encodings.
*/
flag ieee = 1;
MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
@ -3648,9 +3658,11 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
/* Half precision floats come in two formats: standard
IEEE and "ARM" format. The latter gains extra exponent
range by omitting the NaN/Inf encodings. */
/*
* Half precision floats come in two formats: standard
* IEEE and "ARM" format. The latter gains extra exponent
* range by omitting the NaN/Inf encodings.
*/
flag ieee = 1;
MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);