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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO

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I previously fixed this for PMINTENSET_EL1, but missed these.

Backports commit fc5f6856a02168864a5c1a46866a12839322222f from qemu
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Aaron Lindsay 2018-10-23 12:55:57 -04:00 committed by Lioncash
parent 0595aa5ade
commit 10c6887e0b
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target/arm/helper.c
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@ -1246,9 +1246,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
access_tpm, NULL, pmintenset_write, NULL, raw_write },
{ "PMINTENCLR", 15,9,14, 0,0,2, 0,
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
ARM_CP_ALIAS | ARM_CP_IO, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
access_tpm, NULL, pmintenclr_write, },
{ "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
{ "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS | ARM_CP_IO,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
access_tpm, NULL, pmintenclr_write },
{ "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,