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target/arm: Convert T16 add pc/sp (immediate)
Backports commit 1cb1323433dca657a42483b2291c1ae923a91726 from qemu
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@ -23,6 +23,7 @@
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&s_rrr_shr !extern s rn rd rm rs shty
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&s_rrr_shr !extern s rn rd rm rs shty
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&s_rri_rot !extern s rn rd imm rot
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&s_rri_rot !extern s rn rd imm rot
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&s_rrrr !extern s rd rn rm ra
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&s_rrrr !extern s rd rn rm ra
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&ri !extern rd imm
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&ldst_rr !extern p w u rn rt rm shimm shtype
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&ldst_rr !extern p w u rn rt rm shimm shtype
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&ldst_ri !extern p w u rn rt imm
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&ldst_ri !extern p w u rn rt imm
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@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2
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STR_ri 10010 ... ........ @ldst_spec_i rn=13
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STR_ri 10010 ... ........ @ldst_spec_i rn=13
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LDR_ri 10011 ... ........ @ldst_spec_i rn=13
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LDR_ri 10011 ... ........ @ldst_spec_i rn=13
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# Add PC/SP (immediate)
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ADR 10100 rd:3 ........ imm=%imm8_0x4
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ADD_rri 10101 rd:3 ........ \
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&s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
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@ -11220,19 +11220,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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case 7: /* load/store byte immediate offset, in decodetree */
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case 7: /* load/store byte immediate offset, in decodetree */
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case 8: /* load/store halfword immediate offset, in decodetree */
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case 8: /* load/store halfword immediate offset, in decodetree */
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case 9: /* load/store from stack, in decodetree */
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case 9: /* load/store from stack, in decodetree */
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case 10: /* add PC/SP (immediate), in decodetree */
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goto illegal_op;
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goto illegal_op;
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case 10:
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/*
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* 0b1010_xxxx_xxxx_xxxx
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* - Add PC/SP (immediate)
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*/
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rd = (insn >> 8) & 7;
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val = (insn & 0xff) * 4;
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tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
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store_reg(s, rd, tmp);
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break;
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case 11:
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case 11:
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/* misc */
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/* misc */
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op = (insn >> 8) & 0xf;
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op = (insn >> 8) & 0xf;
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