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target/arm: Split out FPSCR.QC to a vector field
Change the representation of this field such that it is easy to set from vector code. Backports commit a4d5846245c5e029e5aa3945a9bda1de1c3fedbf from qemu
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356b70e931
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10d468f601
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@ -568,11 +568,13 @@ typedef struct CPUARMState {
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ARMPredicateReg preg_tmp;
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ARMPredicateReg preg_tmp;
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#endif
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#endif
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uint32_t xregs[16];
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/* We store these fpcsr fields separately for convenience. */
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/* We store these fpcsr fields separately for convenience. */
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uint32_t QEMU_ALIGNED(16, qc[4]);
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int vec_len;
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int vec_len;
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int vec_stride;
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int vec_stride;
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uint32_t xregs[16];
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/* Scratch space for aa32 neon expansion. */
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/* Scratch space for aa32 neon expansion. */
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uint32_t scratch[8];
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uint32_t scratch[8];
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@ -1369,6 +1371,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
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#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
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#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
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#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
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#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
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#define FPCR_DN (1 << 25) /* Default NaN enable bit */
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#define FPCR_DN (1 << 25) /* Default NaN enable bit */
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#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
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static inline uint32_t vfp_get_fpsr(CPUARMState *env)
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static inline uint32_t vfp_get_fpsr(CPUARMState *env)
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{
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{
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@ -11779,8 +11779,7 @@ static inline int vfp_exceptbits_from_host(int host_bits)
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uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
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uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
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{
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{
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int i;
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uint32_t i, fpscr;
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uint32_t fpscr;
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fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
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fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
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| (env->vfp.vec_len << 16)
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| (env->vfp.vec_len << 16)
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@ -11792,6 +11791,10 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
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i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
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i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
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& ~float_flag_input_denormal);
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& ~float_flag_input_denormal);
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fpscr |= vfp_exceptbits_from_host(i);
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fpscr |= vfp_exceptbits_from_host(i);
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i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
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fpscr |= i ? FPCR_QC : 0;
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return fpscr;
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return fpscr;
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}
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}
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@ -11838,10 +11841,19 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
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* (which are stored in fp_status), and the other RES0 bits
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* (which are stored in fp_status), and the other RES0 bits
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* in between, then we clear all of the low 16 bits.
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* in between, then we clear all of the low 16 bits.
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*/
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*/
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env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000;
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env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
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env->vfp.vec_len = (val >> 16) & 7;
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env->vfp.vec_len = (val >> 16) & 7;
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env->vfp.vec_stride = (val >> 20) & 3;
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env->vfp.vec_stride = (val >> 20) & 3;
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/*
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* The bit we set within fpscr_q is arbitrary; the register as a
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* whole being zero/non-zero is what counts.
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*/
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env->vfp.qc[0] = val & FPCR_QC;
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env->vfp.qc[1] = 0;
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env->vfp.qc[2] = 0;
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env->vfp.qc[3] = 0;
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changed ^= val;
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changed ^= val;
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if (changed & (3 << 22)) {
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if (changed & (3 << 22)) {
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i = (val >> 22) & 3;
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i = (val >> 22) & 3;
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@ -16,7 +16,7 @@
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#define SIGNBIT (uint32_t)0x80000000
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#define SIGNBIT (uint32_t)0x80000000
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#define SIGNBIT64 ((uint64_t)1 << 63)
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#define SIGNBIT64 ((uint64_t)1 << 63)
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#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
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#define SET_QC() env->vfp.qc[0] = 1
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#define NEON_TYPE1(name, type) \
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#define NEON_TYPE1(name, type) \
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typedef struct \
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typedef struct \
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@ -37,7 +37,7 @@
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#define H4(x) (x)
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#define H4(x) (x)
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#endif
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#endif
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#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
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#define SET_QC() env->vfp.qc[0] = 1
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static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
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static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
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{
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{
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