mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-23 12:25:32 +00:00
target-i386: Move breakpoint related functions to new file
Backports commit ba4b5c65a98ea91dc3b13e42dd9404808c999dda from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
fb2fe4580f
commit
10e0920fa0
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@ -1,4 +1,4 @@
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obj-y += translate.o helper.o cpu.o
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obj-y += translate.o helper.o cpu.o bpt_helper.o
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obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o
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obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o
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obj-$(CONFIG_SOFTMMU) += arch_memory_mapping.o
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182
qemu/target-i386/bpt_helper.c
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182
qemu/target-i386/bpt_helper.c
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@ -0,0 +1,182 @@
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/*
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* i386 breakpoint helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/helper-proto.h"
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void hw_breakpoint_insert(CPUX86State *env, int index)
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{
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CPUState *cs = CPU(x86_env_get_cpu(env));
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int type = 0, err = 0;
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case DR7_TYPE_BP_INST:
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if (hw_breakpoint_enabled(env->dr[7], index)) {
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err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
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&env->cpu_breakpoint[index]);
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}
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break;
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case DR7_TYPE_DATA_WR:
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type = BP_CPU | BP_MEM_WRITE;
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break;
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case DR7_TYPE_IO_RW:
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/* No support for I/O watchpoints yet */
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break;
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case DR7_TYPE_DATA_RW:
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type = BP_CPU | BP_MEM_ACCESS;
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break;
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}
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if (type != 0) {
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err = cpu_watchpoint_insert(cs, env->dr[index],
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hw_breakpoint_len(env->dr[7], index),
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type, &env->cpu_watchpoint[index]);
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}
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if (err) {
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env->cpu_breakpoint[index] = NULL;
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}
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}
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void hw_breakpoint_remove(CPUX86State *env, int index)
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{
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CPUState *cs;
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if (!env->cpu_breakpoint[index]) {
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return;
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}
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cs = CPU(x86_env_get_cpu(env));
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case DR7_TYPE_BP_INST:
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if (hw_breakpoint_enabled(env->dr[7], index)) {
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cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
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}
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break;
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case DR7_TYPE_DATA_WR:
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case DR7_TYPE_DATA_RW:
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
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break;
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case DR7_TYPE_IO_RW:
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/* No support for I/O watchpoints yet */
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break;
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}
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}
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bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
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{
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target_ulong dr6;
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int reg;
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bool hit_enabled = false;
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dr6 = env->dr[6] & ~0xf;
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for (reg = 0; reg < DR7_MAX_BP; reg++) {
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bool bp_match = false;
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bool wp_match = false;
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switch (hw_breakpoint_type(env->dr[7], reg)) {
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case DR7_TYPE_BP_INST:
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if (env->dr[reg] == env->eip) {
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bp_match = true;
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}
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break;
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case DR7_TYPE_DATA_WR:
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case DR7_TYPE_DATA_RW:
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if (env->cpu_watchpoint[reg] &&
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env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
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wp_match = true;
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}
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break;
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case DR7_TYPE_IO_RW:
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break;
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}
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if (bp_match || wp_match) {
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dr6 |= 1ULL << reg;
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if (hw_breakpoint_enabled(env->dr[7], reg)) {
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hit_enabled = true;
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}
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}
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}
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if (hit_enabled || force_dr6_update) {
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env->dr[6] = dr6;
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}
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return hit_enabled;
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}
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void breakpoint_handler(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs->uc, cs);
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CPUX86State *env = &cpu->env;
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CPUBreakpoint *bp;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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cs->watchpoint_hit = NULL;
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if (check_hw_breakpoints(env, false)) {
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raise_exception(env, EXCP01_DB);
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} else {
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cpu_resume_from_signal(cs, NULL);
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}
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}
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} else {
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QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
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if (bp->pc == env->eip) {
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if (bp->flags & BP_CPU) {
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check_hw_breakpoints(env, true);
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raise_exception(env, EXCP01_DB);
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}
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break;
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}
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}
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}
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}
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void helper_single_step(CPUX86State *env)
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{
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#ifndef CONFIG_USER_ONLY
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check_hw_breakpoints(env, true);
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(env, EXCP01_DB);
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}
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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{
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#ifndef CONFIG_USER_ONLY
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int i;
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if (reg < 4) {
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hw_breakpoint_remove(env, reg);
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env->dr[reg] = t0;
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hw_breakpoint_insert(env, reg);
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} else if (reg == 7) {
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_remove(env, i);
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}
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env->dr[7] = t0;
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_insert(env, i);
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}
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} else {
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env->dr[reg] = t0;
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}
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#endif
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}
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@ -916,134 +916,6 @@ out:
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return pte | page_offset;
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}
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void hw_breakpoint_insert(CPUX86State *env, int index)
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{
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CPUState *cs = CPU(x86_env_get_cpu(env));
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int type = 0, err = 0;
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case DR7_TYPE_BP_INST:
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if (hw_breakpoint_enabled(env->dr[7], index)) {
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err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
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&env->cpu_breakpoint[index]);
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}
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break;
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case DR7_TYPE_DATA_WR:
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type = BP_CPU | BP_MEM_WRITE;
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break;
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case DR7_TYPE_IO_RW:
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/* No support for I/O watchpoints yet */
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break;
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case DR7_TYPE_DATA_RW:
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type = BP_CPU | BP_MEM_ACCESS;
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break;
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}
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if (type != 0) {
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err = cpu_watchpoint_insert(cs, env->dr[index],
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hw_breakpoint_len(env->dr[7], index),
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type, &env->cpu_watchpoint[index]);
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}
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if (err) {
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env->cpu_breakpoint[index] = NULL;
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}
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}
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void hw_breakpoint_remove(CPUX86State *env, int index)
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{
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CPUState *cs;
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if (!env->cpu_breakpoint[index]) {
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return;
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}
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cs = CPU(x86_env_get_cpu(env));
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switch (hw_breakpoint_type(env->dr[7], index)) {
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case DR7_TYPE_BP_INST:
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if (hw_breakpoint_enabled(env->dr[7], index)) {
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cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
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}
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break;
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case DR7_TYPE_DATA_WR:
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case DR7_TYPE_DATA_RW:
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
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break;
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case DR7_TYPE_IO_RW:
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/* No support for I/O watchpoints yet */
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break;
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}
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}
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bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
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{
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target_ulong dr6;
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int reg;
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bool hit_enabled = false;
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dr6 = env->dr[6] & ~0xf;
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for (reg = 0; reg < DR7_MAX_BP; reg++) {
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bool bp_match = false;
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bool wp_match = false;
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switch (hw_breakpoint_type(env->dr[7], reg)) {
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case DR7_TYPE_BP_INST:
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if (env->dr[reg] == env->eip) {
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bp_match = true;
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}
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break;
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case DR7_TYPE_DATA_WR:
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case DR7_TYPE_DATA_RW:
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if (env->cpu_watchpoint[reg] &&
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env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
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wp_match = true;
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}
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break;
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case DR7_TYPE_IO_RW:
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break;
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}
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if (bp_match || wp_match) {
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dr6 |= 1ULL << reg;
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if (hw_breakpoint_enabled(env->dr[7], reg)) {
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hit_enabled = true;
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}
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}
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}
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if (hit_enabled || force_dr6_update) {
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env->dr[6] = dr6;
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}
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return hit_enabled;
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}
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void breakpoint_handler(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs->uc, cs);
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CPUX86State *env = &cpu->env;
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CPUBreakpoint *bp;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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cs->watchpoint_hit = NULL;
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if (check_hw_breakpoints(env, false)) {
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raise_exception(env, EXCP01_DB);
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} else {
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cpu_resume_from_signal(cs, NULL);
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}
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}
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} else {
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QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
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if (bp->pc == env->eip) {
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if (bp->flags & BP_CPU) {
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check_hw_breakpoints(env, true);
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raise_exception(env, EXCP01_DB);
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}
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break;
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}
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}
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}
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}
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typedef struct MCEInjectionParams {
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X86CPU *cpu;
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int bank;
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@ -64,15 +64,6 @@ void helper_into(CPUX86State *env, int next_eip_addend)
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}
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}
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void helper_single_step(CPUX86State *env)
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{
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#ifndef CONFIG_USER_ONLY
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check_hw_breakpoints(env, true);
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(env, EXCP01_DB);
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}
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void helper_cpuid(CPUX86State *env)
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{
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uint32_t eax, ebx, ecx, edx;
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@ -96,10 +87,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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{
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}
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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{
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}
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#else
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target_ulong helper_read_crN(CPUX86State *env, int reg)
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{
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@ -145,27 +132,6 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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break;
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}
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}
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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{
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int i;
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if (reg < 4) {
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hw_breakpoint_remove(env, reg);
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env->dr[reg] = t0;
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hw_breakpoint_insert(env, reg);
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} else if (reg == 7) {
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_remove(env, i);
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}
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env->dr[7] = t0;
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_insert(env, i);
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}
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} else {
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env->dr[reg] = t0;
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}
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}
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#endif
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void helper_lmsw(CPUX86State *env, target_ulong t0)
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