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target/arm/translate-a64: Don't underdecode add/sub extended register

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In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.

Backports commit 4f61106614410945b1d1c93081544ad5b13044fc from qemu
This commit is contained in:
Peter Maydell 2019-02-03 17:37:37 -05:00 committed by Lioncash
parent decebb5936
commit 1128b4d77d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 1 deletions
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qemu/target/arm/translate-a64.c
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@ -4283,6 +4283,7 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
int imm3 = extract32(insn, 10, 3);
int option = extract32(insn, 13, 3);
int rm = extract32(insn, 16, 5);
int opt = extract32(insn, 22, 2);
bool setflags = extract32(insn, 29, 1);
bool sub_op = extract32(insn, 30, 1);
bool sf = extract32(insn, 31, 1);
@ -4291,7 +4292,7 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
TCGv_i64 tcg_rd;
TCGv_i64 tcg_result;
if (imm3 > 4) {
if (imm3 > 4 || opt != 0) {
unallocated_encoding(s);
return;
}