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target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL
It is incorrect to call arm_el_is_aa64() function for unimplemented EL. This patch fixes several attempts to do so. Backports commit 2cde031f5a34996bab32571a26b1a6bcf3e5b5d9 from qemu
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04992f0fb3
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@ -1030,11 +1030,11 @@ static inline bool access_secure_reg(CPUARMState *env)
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*/
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#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
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A32_BANKED_REG_GET((_env), _regname, \
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((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
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(arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
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#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
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A32_BANKED_REG_SET((_env), _regname, \
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((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \
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(arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
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(_val))
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void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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@ -1601,7 +1601,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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* interrupt.
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*/
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if ((target_el > cur_el) && (target_el != 1)) {
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if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) {
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/* ARM_FEATURE_AARCH64 enabled means the highest EL is AArch64.
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* This code currently assumes that EL2 is not implemented
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* (and so that highest EL will be 3 and the target_el also 3).
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*/
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if (arm_feature(env, ARM_FEATURE_AARCH64) ||
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((scr || hcr) && (!secure))) {
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unmasked = 1;
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}
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}
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@ -4586,11 +4586,22 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
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uint32_t cur_el, bool secure)
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{
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CPUARMState *env = cs->env_ptr;
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int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
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int rw;
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int scr;
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int hcr;
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int target_el;
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int is64 = arm_el_is_aa64(env, 3);
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/* Is the highest EL AArch64? */
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int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
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} else {
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/* Either EL2 is the highest EL (and so the EL2 register width
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* is given by is64); or there is no EL2 or EL3, in which case
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* the value of 'rw' does not affect the table lookup anyway.
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*/
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rw = is64;
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}
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switch (excp_idx) {
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case EXCP_IRQ:
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