yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-24 22:15:07 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL

Browse source 
It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
This patch fixes several attempts to do so.

Backports commit 2cde031f5a34996bab32571a26b1a6bcf3e5b5d9 from qemu
This commit is contained in:
Sergey Sorokin 2018-02-16 14:39:38 -05:00 committed by Lioncash
parent 04992f0fb3
commit 1152631b4b
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 21 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
qemu/target-arm/cpu.h
View file

@ -1030,11 +1030,11 @@ static inline bool access_secure_reg(CPUARMState *env)
*/ */
#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
A32_BANKED_REG_GET((_env), _regname, \ A32_BANKED_REG_GET((_env), _regname, \
((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
A32_BANKED_REG_SET((_env), _regname, \ A32_BANKED_REG_SET((_env), _regname, \
((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
(_val)) (_val))
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@ -1601,7 +1601,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
* interrupt. * interrupt.
*/ */
if ((target_el > cur_el) && (target_el != 1)) { if ((target_el > cur_el) && (target_el != 1)) {
if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) { /* ARM_FEATURE_AARCH64 enabled means the highest EL is AArch64.
* This code currently assumes that EL2 is not implemented
* (and so that highest EL will be 3 and the target_el also 3).
*/
if (arm_feature(env, ARM_FEATURE_AARCH64) ||
((scr || hcr) && (!secure))) {
unmasked = 1; unmasked = 1;
} }
} }

15
qemu/target-arm/helper.c
View file

@ -4586,11 +4586,22 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure) uint32_t cur_el, bool secure)
{ {
CPUARMState *env = cs->env_ptr; CPUARMState *env = cs->env_ptr;
int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); int rw;
int scr; int scr;
int hcr; int hcr;
int target_el; int target_el;
int is64 = arm_el_is_aa64(env, 3); /* Is the highest EL AArch64? */
int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
if (arm_feature(env, ARM_FEATURE_EL3)) {
rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
} else {
/* Either EL2 is the highest EL (and so the EL2 register width
* is given by is64); or there is no EL2 or EL3, in which case
* the value of 'rw' does not affect the table lookup anyway.
*/
rw = is64;
}
switch (excp_idx) { switch (excp_idx) {
case EXCP_IRQ: case EXCP_IRQ: