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https://github.com/yuzu-emu/unicorn.git
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tcg: Add tcg_gen_gvec_5_ptr
Extend the vector generator infrastructure to handle 5 vector arguments. Backports commit 2445971604c1cfd3ec484457159f4ac300fb04d2 from qemu
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_aarch64
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_aarch64
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#define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_aarch64
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64eb
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64eb
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64eb
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_aarch64eb
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_aarch64eb
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#define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64eb
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_aarch64eb
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_arm
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_arm
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_arm
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_arm
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_arm
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#define tcg_gen_gvec_add tcg_gen_gvec_add_arm
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_arm
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_armeb
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_armeb
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_armeb
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_armeb
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_armeb
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#define tcg_gen_gvec_add tcg_gen_gvec_add_armeb
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_armeb
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@ -2886,6 +2886,7 @@ symbols = (
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'tcg_gen_gvec_4_ool',
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'tcg_gen_gvec_4_ptr',
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'tcg_gen_gvec_5_ool',
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'tcg_gen_gvec_5_ptr',
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'tcg_gen_gvec_abs',
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'tcg_gen_gvec_add',
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'tcg_gen_gvec_addi',
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_m68k
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_m68k
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_m68k
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_m68k
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_m68k
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#define tcg_gen_gvec_add tcg_gen_gvec_add_m68k
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_m68k
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mips
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips
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#define tcg_gen_gvec_add tcg_gen_gvec_add_mips
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mips64
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips64
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#define tcg_gen_gvec_add tcg_gen_gvec_add_mips64
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips64
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64el
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64el
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64el
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mips64el
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips64el
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#define tcg_gen_gvec_add tcg_gen_gvec_add_mips64el
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips64el
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mipsel
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mipsel
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mipsel
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_mipsel
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mipsel
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#define tcg_gen_gvec_add tcg_gen_gvec_add_mipsel
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_mipsel
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_powerpc
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_powerpc
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_powerpc
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_powerpc
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_powerpc
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#define tcg_gen_gvec_add tcg_gen_gvec_add_powerpc
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_powerpc
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv32
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv32
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv32
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_riscv32
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv32
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#define tcg_gen_gvec_add tcg_gen_gvec_add_riscv32
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv32
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv64
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv64
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv64
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_riscv64
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv64
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#define tcg_gen_gvec_add tcg_gen_gvec_add_riscv64
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv64
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_sparc
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_sparc
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#define tcg_gen_gvec_add tcg_gen_gvec_add_sparc
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_sparc
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc64
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc64
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc64
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_sparc64
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_sparc64
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#define tcg_gen_gvec_add tcg_gen_gvec_add_sparc64
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_sparc64
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@ -290,6 +290,39 @@ void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with five vector operands
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and an extra pointer operand. */
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void tcg_gen_gvec_5_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
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uint32_t oprsz, uint32_t maxsz, int32_t data,
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gen_helper_gvec_5_ptr *fn)
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{
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TCGv_ptr a0, a1, a2, a3, a4;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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a2 = tcg_temp_new_ptr(s);
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a3 = tcg_temp_new_ptr(s);
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a4 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
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tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
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tcg_gen_addi_ptr(s, a4, s->cpu_env, eofs);
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fn(s, a0, a1, a2, a3, a4, ptr, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_ptr(s, a2);
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tcg_temp_free_ptr(s, a3);
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tcg_temp_free_ptr(s, a4);
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tcg_temp_free_i32(s, desc);
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}
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/* Return true if we want to implement something of OPRSZ bytes
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in units of LNSZ. This limits the expansion of inline code. */
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static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
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@ -83,6 +83,13 @@ void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
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uint32_t maxsz, int32_t data,
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gen_helper_gvec_4_ptr *fn);
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typedef void gen_helper_gvec_5_ptr(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
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TCGv_ptr, TCGv_ptr, TCGv_i32);
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void tcg_gen_gvec_5_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, uint32_t eofs, TCGv_ptr ptr,
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uint32_t oprsz, uint32_t maxsz, int32_t data,
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gen_helper_gvec_5_ptr *fn);
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/* Expand a gvec operation. Either inline or out-of-line depending on
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the actual vector size and the operations supported by the host. */
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typedef struct {
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@ -2880,6 +2880,7 @@
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_x86_64
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_x86_64
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_x86_64
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_x86_64
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#define tcg_gen_gvec_abs tcg_gen_gvec_abs_x86_64
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#define tcg_gen_gvec_add tcg_gen_gvec_add_x86_64
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_x86_64
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