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target/arm: Add and use defines for EXCRET constants

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The exception-return magic values get some new bits in v8M, which
makes some bit definitions for them worthwhile.

We don't use the bit definitions for the switch on the low bits
which checks the return type for v7M, because this is defined
in the v7M ARM ARM as a set of valid values rather than via
per-bit checks.

Backports commit 4d1e7a4745c050f7ccac49a1c01437526b5130b5 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 23:12:35 -05:00 committed by Lioncash
parent aa71933721
commit 1301cb1771
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 19 additions and 5 deletions
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14
qemu/target/arm/helper.c
View file

@ -5502,7 +5502,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
" previous exception %d\n", " previous exception %d\n",
type, env->v7m.exception); type, env->v7m.exception);
if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception "
"exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type);
} }
@ -5516,7 +5516,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
*/ */
/* Unicorn: commented out /* Unicorn: commented out
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
int es = type & 1; int es = type & R_V7M_EXCRET_ES_MASK;
if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {
env->v7m.faultmask[es] = 0; env->v7m.faultmask[es] = 0;
} }
@ -5763,12 +5763,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */ return; /* Never happens. Keep compiler happy. */
} }
lr = 0xfffffff1; lr = R_V7M_EXCRET_RES1_MASK |
R_V7M_EXCRET_S_MASK |
R_V7M_EXCRET_DCRS_MASK |
R_V7M_EXCRET_FTYPE_MASK |
R_V7M_EXCRET_ES_MASK;
if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) {
lr |= 4; lr |= R_V7M_EXCRET_SPSEL_MASK;
} }
if (!arm_v7m_is_handler_mode(env)) { if (!arm_v7m_is_handler_mode(env)) {
lr |= 8; lr |= R_V7M_EXCRET_MODE_MASK;
} }
v7m_push_stack(cpu); v7m_push_stack(cpu);

10
qemu/target/arm/internals.h
View file

@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1)
FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1)
FIELD(V7M_CONTROL, FPCA, 2, 1) FIELD(V7M_CONTROL, FPCA, 2, 1)
/* Bit definitions for v7M exception return payload */
FIELD(V7M_EXCRET, ES, 0, 1)
FIELD(V7M_EXCRET, RES0, 1, 1)
FIELD(V7M_EXCRET, SPSEL, 2, 1)
FIELD(V7M_EXCRET, MODE, 3, 1)
FIELD(V7M_EXCRET, FTYPE, 4, 1)
FIELD(V7M_EXCRET, DCRS, 5, 1)
FIELD(V7M_EXCRET, S, 6, 1)
FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
/* /*
* For AArch64, map a given EL to an index in the banked_spsr array. * For AArch64, map a given EL to an index in the banked_spsr array.
* Note that this mapping and the AArch32 mapping defined in bank_number() * Note that this mapping and the AArch32 mapping defined in bank_number()