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target/riscv: Add hfence instructions
Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu
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@ -63,20 +63,25 @@
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@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
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@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
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@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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# *** Privileged Instructions ***
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ecall 000000000000 00000 000 00000 1110011
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ebreak 000000000001 00000 000 00000 1110011
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uret 0000000 00010 00000 000 00000 1110011
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sret 0001000 00010 00000 000 00000 1110011
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hret 0010000 00010 00000 000 00000 1110011
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mret 0011000 00010 00000 000 00000 1110011
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wfi 0001000 00101 00000 000 00000 1110011
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sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
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sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
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ecall 000000000000 00000 000 00000 1110011
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ebreak 000000000001 00000 000 00000 1110011
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uret 0000000 00010 00000 000 00000 1110011
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sret 0001000 00010 00000 000 00000 1110011
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hret 0010000 00010 00000 000 00000 1110011
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mret 0011000 00010 00000 000 00000 1110011
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wfi 0001000 00101 00000 000 00000 1110011
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hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
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hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
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sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
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sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
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# *** RV32I Base Instruction Set ***
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lui .................... ..... 0110111 @u
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@ -113,3 +113,45 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
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#endif
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return false;
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}
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static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
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{
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#ifndef CONFIG_USER_ONLY
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
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has_ext(ctx, RVH)) {
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/* Hpervisor extensions exist */
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/*
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* if (env->priv == PRV_M ||
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* (env->priv == PRV_S &&
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* !riscv_cpu_virt_enabled(env) &&
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* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
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*/
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gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
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return true;
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/* } */
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}
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#endif
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return false;
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}
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static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
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{
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#ifndef CONFIG_USER_ONLY
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
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has_ext(ctx, RVH)) {
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/* Hpervisor extensions exist */
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/*
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* if (env->priv == PRV_M ||
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* (env->priv == PRV_S &&
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* !riscv_cpu_virt_enabled(env) &&
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* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
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*/
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gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
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return true;
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/* } */
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}
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#endif
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return false;
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}
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