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target/riscv: Add hfence instructions

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Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:43:51 -04:00 committed by Lioncash
parent fcc30eac4d
commit 13a7b74827
2 changed files with 56 additions and 9 deletions
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5
qemu/target/riscv/insn32.decode
View file

@ -63,6 +63,9 @@
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@ -75,6 +78,8 @@ sret 0001000 00010 00000 000 00000 1110011
hret 0010000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm

42
qemu/target/riscv/insn_trans/trans_privileged.inc.c
View file

@ -113,3 +113,45 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
#endif
return false;
}
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
* (env->priv == PRV_S &&
* !riscv_cpu_virt_enabled(env) &&
* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
*/
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;
/* } */
}
#endif
return false;
}
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
* (env->priv == PRV_S &&
* !riscv_cpu_virt_enabled(env) &&
* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
*/
gen_helper_tlb_flush(tcg_ctx, tcg_ctx->cpu_env);
return true;
/* } */
}
#endif
return false;
}