mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-02-02 06:21:01 +00:00
target/riscv: add fault-only-first unit stride load
The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Backports commit 022b4ecf775ffeff522eaea4f0d94edcfe00a0a9 from qemu
This commit is contained in:
LIU Zhiwei
Lioncash
parent
887c29bc79
commit
152934bade
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@ -6174,6 +6174,28 @@ riscv_symbols = (
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'helper_vsse_v_h',
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'helper_vsse_v_w',
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'helper_vsse_v_d',
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'helper_vlbff_v_b',
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'helper_vlbff_v_h',
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'helper_vlbff_v_w',
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'helper_vlbff_v_d',
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'helper_vlhff_v_h',
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'helper_vlhff_v_w',
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'helper_vlhff_v_d',
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'helper_vlwff_v_w',
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'helper_vlwff_v_d',
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'helper_vleff_v_b',
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'helper_vleff_v_h',
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'helper_vleff_v_w',
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'helper_vleff_v_d',
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'helper_vlbuff_v_b',
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'helper_vlbuff_v_h',
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'helper_vlbuff_v_w',
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'helper_vlbuff_v_d',
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'helper_vlhuff_v_h',
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'helper_vlhuff_v_w',
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'helper_vlhuff_v_d',
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'helper_vlwuff_v_w',
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'helper_vlwuff_v_d',
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'helper_vlxb_v_b',
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'helper_vlxb_v_h',
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'helper_vlxb_v_w',
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@ -3628,6 +3628,28 @@
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#define helper_vsse_v_h helper_vsse_v_h_riscv32
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#define helper_vsse_v_w helper_vsse_v_w_riscv32
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#define helper_vsse_v_d helper_vsse_v_d_riscv32
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#define helper_vlbff_v_b helper_vlbff_v_b_riscv32
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#define helper_vlbff_v_h helper_vlbff_v_h_riscv32
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#define helper_vlbff_v_w helper_vlbff_v_w_riscv32
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#define helper_vlbff_v_d helper_vlbff_v_d_riscv32
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#define helper_vlhff_v_h helper_vlhff_v_h_riscv32
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#define helper_vlhff_v_w helper_vlhff_v_w_riscv32
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#define helper_vlhff_v_d helper_vlhff_v_d_riscv32
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#define helper_vlwff_v_w helper_vlwff_v_w_riscv32
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#define helper_vlwff_v_d helper_vlwff_v_d_riscv32
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#define helper_vleff_v_b helper_vleff_v_b_riscv32
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#define helper_vleff_v_h helper_vleff_v_h_riscv32
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#define helper_vleff_v_w helper_vleff_v_w_riscv32
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#define helper_vleff_v_d helper_vleff_v_d_riscv32
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#define helper_vlbuff_v_b helper_vlbuff_v_b_riscv32
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#define helper_vlbuff_v_h helper_vlbuff_v_h_riscv32
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#define helper_vlbuff_v_w helper_vlbuff_v_w_riscv32
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#define helper_vlbuff_v_d helper_vlbuff_v_d_riscv32
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#define helper_vlhuff_v_h helper_vlhuff_v_h_riscv32
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#define helper_vlhuff_v_w helper_vlhuff_v_w_riscv32
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#define helper_vlhuff_v_d helper_vlhuff_v_d_riscv32
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#define helper_vlwuff_v_w helper_vlwuff_v_w_riscv32
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#define helper_vlwuff_v_d helper_vlwuff_v_d_riscv32
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#define helper_vlxb_v_b helper_vlxb_v_b_riscv32
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#define helper_vlxb_v_h helper_vlxb_v_h_riscv32
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#define helper_vlxb_v_w helper_vlxb_v_w_riscv32
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@ -3628,6 +3628,28 @@
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#define helper_vsse_v_h helper_vsse_v_h_riscv64
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#define helper_vsse_v_w helper_vsse_v_w_riscv64
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#define helper_vsse_v_d helper_vsse_v_d_riscv64
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#define helper_vlbff_v_b helper_vlbff_v_b_riscv64
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#define helper_vlbff_v_h helper_vlbff_v_h_riscv64
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#define helper_vlbff_v_w helper_vlbff_v_w_riscv64
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#define helper_vlbff_v_d helper_vlbff_v_d_riscv64
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#define helper_vlhff_v_h helper_vlhff_v_h_riscv64
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#define helper_vlhff_v_w helper_vlhff_v_w_riscv64
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#define helper_vlhff_v_d helper_vlhff_v_d_riscv64
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#define helper_vlwff_v_w helper_vlwff_v_w_riscv64
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#define helper_vlwff_v_d helper_vlwff_v_d_riscv64
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#define helper_vleff_v_b helper_vleff_v_b_riscv64
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#define helper_vleff_v_h helper_vleff_v_h_riscv64
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#define helper_vleff_v_w helper_vleff_v_w_riscv64
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#define helper_vleff_v_d helper_vleff_v_d_riscv64
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#define helper_vlbuff_v_b helper_vlbuff_v_b_riscv64
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#define helper_vlbuff_v_h helper_vlbuff_v_h_riscv64
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#define helper_vlbuff_v_w helper_vlbuff_v_w_riscv64
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#define helper_vlbuff_v_d helper_vlbuff_v_d_riscv64
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#define helper_vlhuff_v_h helper_vlhuff_v_h_riscv64
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#define helper_vlhuff_v_w helper_vlhuff_v_w_riscv64
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#define helper_vlhuff_v_d helper_vlhuff_v_d_riscv64
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#define helper_vlwuff_v_w helper_vlwuff_v_w_riscv64
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#define helper_vlwuff_v_d helper_vlwuff_v_d_riscv64
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#define helper_vlxb_v_b helper_vlxb_v_b_riscv64
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#define helper_vlxb_v_h helper_vlxb_v_h_riscv64
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#define helper_vlxb_v_w helper_vlxb_v_w_riscv64
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@ -227,3 +227,26 @@ DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
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@ -226,6 +226,13 @@ vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
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vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
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vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
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vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
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vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
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vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
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vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
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vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
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vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
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vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
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vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
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vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
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vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
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vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
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@ -567,3 +567,77 @@ GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
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/*
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*** unit stride fault-only-first load
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*/
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static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
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gen_helper_ldst_us *fn, DisasContext *s)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_ptr dest, mask;
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TCGv base;
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TCGv_i32 desc;
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TCGLabel *over = gen_new_label(tcg_ctx);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over);
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dest = tcg_temp_new_ptr(tcg_ctx);
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mask = tcg_temp_new_ptr(tcg_ctx);
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base = tcg_temp_new(tcg_ctx);
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desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data));
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gen_get_gpr(s, base, rs1);
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tcg_gen_addi_ptr(tcg_ctx, dest, tcg_ctx->cpu_env, vreg_ofs(s, vd));
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tcg_gen_addi_ptr(tcg_ctx, mask, tcg_ctx->cpu_env, vreg_ofs(s, 0));
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fn(tcg_ctx, dest, mask, base, tcg_ctx->cpu_env, desc);
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tcg_temp_free_ptr(tcg_ctx, dest);
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tcg_temp_free_ptr(tcg_ctx, mask);
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tcg_temp_free(tcg_ctx, base);
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tcg_temp_free_i32(tcg_ctx, desc);
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gen_set_label(tcg_ctx, over);
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return true;
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}
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static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
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{
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uint32_t data = 0;
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gen_helper_ldst_us *fn;
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static gen_helper_ldst_us * const fns[7][4] = {
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{ gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
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gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
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{ NULL, gen_helper_vlhff_v_h,
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gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
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{ NULL, NULL,
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gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
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{ gen_helper_vleff_v_b, gen_helper_vleff_v_h,
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gen_helper_vleff_v_w, gen_helper_vleff_v_d },
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{ gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
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gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
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{ NULL, gen_helper_vlhuff_v_h,
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gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
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{ NULL, NULL,
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gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
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};
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fn = fns[seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, NF, a->nf);
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return ldff_trans(a->rd, a->rs1, data, fn, s);
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}
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GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
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GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
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GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
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GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
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GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
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GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
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GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
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@ -578,3 +578,113 @@ GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
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GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
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GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
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GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
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/*
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*** unit-stride fault-only-fisrt load instructions
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*/
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static inline void
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vext_ldff(void *vd, void *v0, target_ulong base,
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CPURISCVState *env, uint32_t desc,
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vext_ldst_elem_fn *ldst_elem,
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clear_fn *clear_elem,
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uint32_t esz, uint32_t msz, uintptr_t ra)
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{
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void *host;
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uint32_t i, k, vl = 0;
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uint32_t mlen = vext_mlen(desc);
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uint32_t nf = vext_nf(desc);
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uint32_t vm = vext_vm(desc);
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uint32_t vlmax = vext_maxsz(desc) / esz;
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target_ulong addr, offset, remain;
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/* probe every access*/
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for (i = 0; i < env->vl; i++) {
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if (!vm && !vext_elem_mask(v0, mlen, i)) {
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continue;
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}
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addr = base + nf * i * msz;
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if (i == 0) {
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probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
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} else {
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/* if it triggers an exception, no need to check watchpoint */
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remain = nf * msz;
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while (remain > 0) {
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offset = -(addr | TARGET_PAGE_MASK);
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host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
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cpu_mmu_index(env, false));
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if (host) {
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#ifdef CONFIG_USER_ONLY
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if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
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vl = i;
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goto ProbeSuccess;
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}
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#else
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probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
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#endif
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} else {
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vl = i;
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goto ProbeSuccess;
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}
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if (remain <= offset) {
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break;
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}
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remain -= offset;
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addr += offset;
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}
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}
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}
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ProbeSuccess:
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/* load bytes from guest memory */
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if (vl != 0) {
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env->vl = vl;
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}
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for (i = 0; i < env->vl; i++) {
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k = 0;
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if (!vm && !vext_elem_mask(v0, mlen, i)) {
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continue;
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}
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while (k < nf) {
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target_ulong addr = base + (i * nf + k) * msz;
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ldst_elem(env, addr, i + k * vlmax, vd, ra);
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k++;
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}
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}
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/* clear tail elements */
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if (vl != 0) {
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return;
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}
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for (k = 0; k < nf; k++) {
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clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
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}
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}
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#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
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void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
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sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
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}
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GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
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GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
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GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
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GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
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GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
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GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
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GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
|
||||
GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
|
||||
GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
|
||||
GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
|
||||
GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
|
||||
GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
|
||||
GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
|
||||
GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
|
||||
GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
|
||||
GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
|
||||
GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
|
||||
GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
|
||||
GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
|
||||
GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
|
||||
GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
|
||||
GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
|
||||
|
|
|
|||
Loading…
Reference in a new issue