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target-arm: make VBAR banked

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When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.

Backports commit fb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b from qemu
This commit is contained in:
Greg Bellows 2018-02-12 09:40:05 -05:00 committed by Lioncash
parent ccccef3d41
commit 153e7e7331
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 12 additions and 3 deletions
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10
qemu/target-arm/cpu.h
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@ -299,7 +299,15 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */ uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1; uint64_t mair_el1;
uint64_t vbar_el[4]; /* vector base address register */ union { /* vector base address register */
struct {
uint64_t _unused_vbar;
uint64_t vbar_ns;
uint64_t hvbar;
uint64_t vbar_s;
};
uint64_t vbar_el[4];
};
uint32_t mvbar; /* (monitor) vector base address register */ uint32_t mvbar; /* (monitor) vector base address register */
uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */ uint64_t contextidr_el1; /* Context ID. */

5
qemu/target-arm/helper.c
View file

@ -2778,7 +2778,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_VBAR)) { if (arm_feature(env, ARM_FEATURE_VBAR)) {
ARMCPRegInfo vbar_cp_reginfo[] = { ARMCPRegInfo vbar_cp_reginfo[] = {
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH, { "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[1]), {0, 0}, 0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) },
NULL, NULL, vbar_write, }, NULL, NULL, vbar_write, },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
@ -3898,7 +3899,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
* This register is only followed in non-monitor mode, and is banked. * This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid. * Note: only bits 31:5 are valid.
*/ */
addr += env->cp15.vbar_el[1]; addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
} }
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {