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target/arm: Fix execution of ARM instructions

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Previously we'd be checking prior to the actual decoding if we were at
the ending address. This worked fine using the old model of the
translation process in qemu. However, this causes the wrong behavior to
occur in both ARM and Thumb/Thumb-2 modes using the newer translator
model.

Given the translator itself checks for the end address already, this
needs to be placed within arm_post_translate_insn().

This prevents the emulation process being off-by-one as well when it
comes to actually executing the instructions.
This commit is contained in:
Lioncash 2019-02-28 18:49:18 -05:00
parent dcc9420555
commit 15440a83c5
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 7 deletions
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14
qemu/target/arm/translate.c
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@ -12595,13 +12595,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
TCGv_i32 tmp2;
TCGv_i32 addr;
// Unicorn: end address tells us to stop emulation
if (s->pc == s->uc->addr_end) {
// imitate WFI instruction to halt emulation
s->base.is_jmp = DISAS_WFI;
return;
}
// Unicorn: trace this instruction on request
if (HOOK_EXISTS_BOUNDED(s->uc, UC_HOOK_CODE, s->pc)) {
// determine instruction size (Thumb/Thumb2)
@ -13666,6 +13659,13 @@ static void arm_post_translate_insn(DisasContext *dc)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
// Unicorn: end address tells us to stop emulation
if (dc->pc == dc->uc->addr_end) {
// imitate WFI instruction to halt emulation
dc->base.is_jmp = DISAS_WFI;
return;
}
if (dc->condjmp && !dc->base.is_jmp) {
gen_set_label(tcg_ctx, dc->condlabel);
dc->condjmp = 0;