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target/riscv: Update the CSRs to the v0.6 Hyp extension

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Backports 543ba53157f9003eaa9b802d44c577c5814e232c
This commit is contained in:
Alistair Francis 2021-03-08 13:33:01 -05:00 committed by Lioncash
parent bf52a9b17e
commit 1551a961ba
1 changed files with 8 additions and 7 deletions
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15
qemu/target/riscv/cpu_bits.h
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@ -437,16 +437,17 @@
#endif
/* hstatus CSR bits */
#define HSTATUS_SPRV 0x00000001
#define HSTATUS_STL 0x00000040
#define HSTATUS_VSBE 0x00000020
#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
#define HSTATUS_SP2P 0x00000100
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_SPVP 0x00000100
#define HSTATUS_HU 0x00000200
#define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPVP 0x00000100
#if defined(TARGET_RISCV64)
#define HSTATUS_VSXL 0x300000000
#endif
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL