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target-i386: Perform set/reset_inhibit_irq inline

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With helpers that can be reused for other things.

Backports commit 7f0b7141b4c7deab51efd8ee1e83eab2d9b7a9ea from qemu
This commit is contained in:
Richard Henderson 2018-02-20 13:34:41 -05:00 committed by Lioncash
parent cacb60b57b
commit 159e837a6c
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 35 additions and 22 deletions
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10
qemu/target-i386/cc_helper.c
View file

@ -378,13 +378,3 @@ void helper_sti_vm(CPUX86State *env)
} }
} }
#endif #endif
void helper_set_inhibit_irq(CPUX86State *env)
{
env->hflags |= HF_INHIBIT_IRQ_MASK;
}
void helper_reset_inhibit_irq(CPUX86State *env)
{
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
}

2
qemu/target-i386/helper.h
View file

@ -64,8 +64,6 @@ DEF_HELPER_1(cli, void, env)
DEF_HELPER_1(sti, void, env) DEF_HELPER_1(sti, void, env)
DEF_HELPER_1(clac, void, env) DEF_HELPER_1(clac, void, env)
DEF_HELPER_1(stac, void, env) DEF_HELPER_1(stac, void, env)
DEF_HELPER_1(set_inhibit_irq, void, env)
DEF_HELPER_1(reset_inhibit_irq, void, env)
DEF_HELPER_3(boundw, void, env, tl, int) DEF_HELPER_3(boundw, void, env, tl, int)
DEF_HELPER_3(boundl, void, env, tl, int) DEF_HELPER_3(boundl, void, env, tl, int)
DEF_HELPER_1(rsm, void, env) DEF_HELPER_1(rsm, void, env)

45
qemu/target-i386/translate.c
View file

@ -2715,16 +2715,44 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip)
s->is_jmp = DISAS_TB_JUMP; s->is_jmp = DISAS_TB_JUMP;
} }
static void gen_set_hflag(DisasContext *s, uint32_t mask)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr cpu_env = tcg_ctx->cpu_env;
if ((s->flags & mask) == 0) {
TCGv_i32 t = tcg_temp_new_i32(tcg_ctx);
tcg_gen_ld_i32(tcg_ctx, t, cpu_env, offsetof(CPUX86State, hflags));
tcg_gen_ori_i32(tcg_ctx, t, t, mask);
tcg_gen_st_i32(tcg_ctx, t, cpu_env, offsetof(CPUX86State, hflags));
tcg_temp_free_i32(tcg_ctx, t);
s->flags |= mask;
}
}
static void gen_reset_hflag(DisasContext *s, uint32_t mask)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr cpu_env = tcg_ctx->cpu_env;
if (s->flags & mask) {
TCGv_i32 t = tcg_temp_new_i32(tcg_ctx);
tcg_gen_ld_i32(tcg_ctx, t, cpu_env, offsetof(CPUX86State, hflags));
tcg_gen_andi_i32(tcg_ctx, t, t, ~mask);
tcg_gen_st_i32(tcg_ctx, t, cpu_env, offsetof(CPUX86State, hflags));
tcg_temp_free_i32(tcg_ctx, t);
s->flags &= ~mask;
}
}
/* generate a generic end of block. Trace exception is also generated /* generate a generic end of block. Trace exception is also generated
if needed */ if needed */
static void gen_eob(DisasContext *s) static void gen_eob(DisasContext *s)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
gen_update_cc_op(s); // qq gen_update_cc_op(s);
if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK);
gen_helper_reset_inhibit_irq(tcg_ctx, tcg_ctx->cpu_env);
}
if (s->tb->flags & HF_RF_MASK) { if (s->tb->flags & HF_RF_MASK) {
gen_helper_reset_rf(tcg_ctx, tcg_ctx->cpu_env); gen_helper_reset_rf(tcg_ctx, tcg_ctx->cpu_env);
} }
@ -5784,8 +5812,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* if reg == SS, inhibit interrupts/trace. */ /* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the /* If several instructions disable interrupts, only the
_first_ does it */ _first_ does it */
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
gen_helper_set_inhibit_irq(tcg_ctx, cpu_env);
s->tf = 0; s->tf = 0;
} }
if (s->is_jmp) { if (s->is_jmp) {
@ -5858,8 +5885,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* if reg == SS, inhibit interrupts/trace */ /* if reg == SS, inhibit interrupts/trace */
/* If several instructions disable interrupts, only the /* If several instructions disable interrupts, only the
_first_ does it */ _first_ does it */
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
gen_helper_set_inhibit_irq(tcg_ctx, cpu_env);
s->tf = 0; s->tf = 0;
} }
if (s->is_jmp) { if (s->is_jmp) {
@ -7416,8 +7442,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
/* interruptions are enabled only the first insn after sti */ /* interruptions are enabled only the first insn after sti */
/* If several instructions disable interrupts, only the /* If several instructions disable interrupts, only the
_first_ does it */ _first_ does it */
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
gen_helper_set_inhibit_irq(tcg_ctx, cpu_env);
/* give a chance to handle pending irqs */ /* give a chance to handle pending irqs */
gen_jmp_im(s, s->pc - s->cs_base); gen_jmp_im(s, s->pc - s->cs_base);
gen_eob(s); gen_eob(s);