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target/mips: Add EVA support to P5600

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Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
configuration, along with the related Segmentation Control (SC) feature
and writable CP0_EBase.WG bit.

This allows it to run Malta EVA kernels.

Backports commit 574da58e4678b3c09048f268821295422d8cde6d from qemu
This commit is contained in:
James Hogan 2018-03-04 01:08:18 -05:00 committed by Lioncash
parent 1ef8c8bd48
commit 16d97568e2
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 4 deletions
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10
qemu/target/mips/translate_init.c
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@ -584,12 +584,14 @@ static const mips_def_t mips_defs[] =
(1 << CP0C1_PC) | (1 << CP0C1_FP),
MIPS_CONFIG2,
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
(1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
(1 << CP0C3_VInt),
MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(0x1c << CP0C4_KScrExist),
0,
MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
(1 << CP0C5_K) | (1 << CP0C5_CV) |
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFR),
@ -613,7 +615,7 @@ static const mips_def_t mips_defs[] =
0,0, 0,0, 0,0, 0,0, 0,0,
(1U << CP0PG_RIE) | (1 << CP0PG_XIE) | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
0,
0,
(1 << CP0EBase_WG),
CPU_MIPS32R5 | ASE_MSA,
MMU_TYPE_R4000,
},