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target/mips: Clean up handling of CP0 register 10
Clean up handling of CP0 register 10. Backports commit 860ffef0477a92f1944f10528887fa5e74e6535d from qemu
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11d02fc0b7
commit
16e817b003
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@ -341,6 +341,7 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG10__ENTRYHI 0
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#define CP0_REG10__GUESTCTL1 4
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#define CP0_REG10__GUESTCTL2 5
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#define CP0_REG10__GUESTCTL3 6
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/* CP0 Register 11 */
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#define CP0_REG11__COMPARE 0
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#define CP0_REG11__GUESTCTL0EXT 4
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@ -7234,7 +7234,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_10:
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switch (sel) {
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case 0:
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case CP0_REG10__ENTRYHI:
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tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
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tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
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register_name = "EntryHi";
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@ -7952,7 +7952,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_10:
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switch (sel) {
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case 0:
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case CP0_REG10__ENTRYHI:
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gen_helper_mtc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, arg);
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register_name = "EntryHi";
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break;
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@ -8707,7 +8707,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_10:
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switch (sel) {
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case 0:
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case CP0_REG10__ENTRYHI:
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tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
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register_name = "EntryHi";
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break;
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@ -9406,7 +9406,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_10:
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switch (sel) {
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case 0:
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case CP0_REG10__ENTRYHI:
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gen_helper_mtc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, arg);
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register_name = "EntryHi";
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break;
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