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target/arm: Implement ARMv8.0-SB

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Backports commit 9888bd1e20425dfe4dcca5dcd1ca2fac8e90ad19 from qemu
This commit is contained in:
Richard Henderson 2019-03-05 22:35:14 -05:00 committed by Lioncash
parent a552a7b2e0
commit 1721e429c2
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GPG key ID: 4E3C3CC1031BA9C7
5 changed files with 49 additions and 0 deletions
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1
qemu/target/arm/cpu.c
View file

@ -1711,6 +1711,7 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
t = FIELD_DP32(t, ID_ISAR6, DP, 1); t = FIELD_DP32(t, ID_ISAR6, DP, 1);
t = FIELD_DP32(t, ID_ISAR6, FHM, 1); t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
t = FIELD_DP32(t, ID_ISAR6, SB, 1);
cpu->isar.id_isar6 = t; cpu->isar.id_isar6 = t;
t = cpu->id_mmfr4; t = cpu->id_mmfr4;

10
qemu/target/arm/cpu.h
View file

@ -3287,6 +3287,11 @@ static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
} }
static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
}
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
{ {
/* /*
@ -3425,6 +3430,11 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
} }
static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
}
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{ {
/* We always set the AdvSIMD and FP fields identically wrt FP16. */ /* We always set the AdvSIMD and FP fields identically wrt FP16. */

2
qemu/target/arm/cpu64.c
View file

@ -263,6 +263,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
cpu->isar.id_aa64isar1 = t; cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64pfr0; t = cpu->isar.id_aa64pfr0;
@ -294,6 +295,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
u = FIELD_DP32(u, ID_ISAR6, DP, 1); u = FIELD_DP32(u, ID_ISAR6, DP, 1);
u = FIELD_DP32(u, ID_ISAR6, FHM, 1); u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
u = FIELD_DP32(u, ID_ISAR6, SB, 1);
cpu->isar.id_isar6 = u; cpu->isar.id_isar6 = u;
// Unicorn: we lie and enable them anyway // Unicorn: we lie and enable them anyway

14
qemu/target/arm/translate-a64.c
View file

@ -1713,7 +1713,21 @@ static void handle_sync(DisasContext *s, uint32_t insn,
reset_btype(s); reset_btype(s);
gen_goto_tb(s, 0, s->pc); gen_goto_tb(s, 0, s->pc);
return; return;
case 7: /* SB */
if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {
goto do_unallocated;
}
/*
* TODO: There is no speculation barrier opcode for TCG;
* MB and end the TB instead.
*/
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC);
gen_goto_tb(s, 0, s->pc);
return;
default: default:
do_unallocated:
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }

22
qemu/target/arm/translate.c
View file

@ -9470,6 +9470,17 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
*/ */
gen_goto_tb(s, 0, s->pc & ~1); gen_goto_tb(s, 0, s->pc & ~1);
return; return;
case 7: /* sb */
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
goto illegal_op;
}
/*
* TODO: There is no speculation barrier opcode
* for TCG; MB and end the TB instead.
*/
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC);
gen_goto_tb(s, 0, s->pc & ~1);
return;
default: default:
goto illegal_op; goto illegal_op;
} }
@ -12084,6 +12095,17 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
*/ */
gen_goto_tb(s, 0, s->pc & ~1); gen_goto_tb(s, 0, s->pc & ~1);
break; break;
case 7: /* sb */
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
goto illegal_op;
}
/*
* TODO: There is no speculation barrier opcode
* for TCG; MB and end the TB instead.
*/
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC);
gen_goto_tb(s, 0, s->pc & ~1);
break;
default: default:
goto illegal_op; goto illegal_op;
} }