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Add ARM MSP, PSP and CONTROL register access (#1071)

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Necessary for NVIC exception emulation from user.

Backports commit 31851280316d37305f412fff42f45bb375999074 from unicorn
This commit is contained in:
yhql 2019-03-08 02:24:39 -05:00 committed by Lioncash
parent 8f688748c4
commit 1723cb1015
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 23 additions and 2 deletions
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3
include/unicorn/arm.h
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@ -134,6 +134,9 @@ typedef enum uc_arm_reg {
UC_ARM_REG_C13_C0_3,
UC_ARM_REG_IPSR,
UC_ARM_REG_MSP,
UC_ARM_REG_PSP,
UC_ARM_REG_CONTROL,
UC_ARM_REG_ENDING, // <-- mark the end of the list or registers
//> alias registers

22
qemu/target/arm/unicorn_arm.c
View file

@ -93,11 +93,20 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
case UC_ARM_REG_FPEXC:
*(int32_t *)value = state->vfp.xregs[ARM_VFP_FPEXC];
break;
case UC_ARM_REG_FPSCR:
*(int32_t *)value = vfp_get_fpscr(state);
break;
case UC_ARM_REG_IPSR:
*(uint32_t *)value = xpsr_read(state) & 0x1ff;
break;
case UC_ARM_REG_FPSCR:
*(int32_t *)value = vfp_get_fpscr(state);
case UC_ARM_REG_MSP:
*(uint32_t *)value = helper_v7m_mrs(state, 8);
break;
case UC_ARM_REG_PSP:
*(uint32_t *)value = helper_v7m_mrs(state, 9);
break;
case UC_ARM_REG_CONTROL:
*(uint32_t *)value = helper_v7m_mrs(state, 20);
break;
}
}
@ -163,6 +172,15 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
case UC_ARM_REG_IPSR:
xpsr_write(state, *(uint32_t *)value, 0x1ff);
break;
case UC_ARM_REG_MSP:
helper_v7m_msr(state, 8, *(uint32_t *)value);
break;
case UC_ARM_REG_PSP:
helper_v7m_msr(state, 9, *(uint32_t *)value);
break;
case UC_ARM_REG_CONTROL:
helper_v7m_msr(state, 20, *(uint32_t *)value);
break;
}
}
}