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target/arm: Use extract2 for EXTR

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This is, after all, how we implement extract2 in tcg/aarch64.

Backports commit 80ac954c369e7e61bd1ed00cef07b63e11f9c734 from qemu
This commit is contained in:
Richard Henderson 2019-05-24 17:58:40 -04:00 committed by Lioncash
parent 0412b3be8a
commit 1778828644
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 20 additions and 18 deletions
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38
qemu/target/arm/translate-a64.c
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@ -4198,25 +4198,27 @@ static void disas_extract(DisasContext *s, uint32_t insn)
} else { } else {
tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, cpu_reg(s, rm)); tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, cpu_reg(s, rm));
} }
} else if (rm == rn) { /* ROR */
tcg_rm = cpu_reg(s, rm);
if (sf) {
tcg_gen_rotri_i64(tcg_ctx, tcg_rd, tcg_rm, imm);
} else {
TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, tcg_rm);
tcg_gen_rotri_i32(tcg_ctx, tmp, tmp, imm);
tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
}
} else { } else {
tcg_rm = read_cpu_reg(s, rm, sf); tcg_rm = cpu_reg(s, rm);
tcg_rn = read_cpu_reg(s, rn, sf); tcg_rn = cpu_reg(s, rn);
tcg_gen_shri_i64(tcg_ctx, tcg_rm, tcg_rm, imm);
tcg_gen_shli_i64(tcg_ctx, tcg_rn, tcg_rn, bitsize - imm); if (sf) {
tcg_gen_or_i64(tcg_ctx, tcg_rd, tcg_rm, tcg_rn); /* Specialization to ROR happens in EXTRACT2. */
if (!sf) { tcg_gen_extract2_i64(tcg_ctx, tcg_rd, tcg_rm, tcg_rn, imm);
tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, tcg_rd); } else {
TCGv_i32 t0 = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, t0, tcg_rm);
if (rm == rn) {
tcg_gen_rotri_i32(tcg_ctx, t0, t0, imm);
} else {
TCGv_i32 t1 = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, t1, tcg_rn);
tcg_gen_extract2_i32(tcg_ctx, t0, t0, t1, imm);
tcg_temp_free_i32(tcg_ctx, t1);
}
tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, t0);
tcg_temp_free_i32(tcg_ctx, t0);
} }
} }
} }