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cpu: move debug_check_watchpoint to tcg_ops

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commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.

Make debug_check_watchpoint optional, and move it to tcg_ops.

Backports c73bdb35a91fb6b17c2c93b1ba381fc88a406f8d
This commit is contained in:
Claudio Fontana 2021-03-04 17:29:26 -05:00 committed by Lioncash
parent 7b0c98c236
commit 18100d1a3b
4 changed files with 10 additions and 16 deletions
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4
qemu/exec.c
View file

@ -881,8 +881,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
if (wp->flags & BP_CPU &&
!cc->debug_check_watchpoint(cpu, wp)) {
if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoint &&
!cc->tcg_ops.debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}

9
qemu/include/qom/cpu.h
View file

@ -140,6 +140,12 @@ typedef struct TcgCpuOperations {
*/
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
} TcgCpuOperations;
/**
@ -173,8 +179,6 @@ typedef struct TcgCpuOperations {
* instead of get_phys_page_debug.
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
* @debug_check_watchpoint: Callback: return true if the architectural
* watchpoint whose address has matched should really fire.
* @vmsd: State description for migration.
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
@ -208,7 +212,6 @@ typedef struct CPUClass {
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
const struct VMStateDescription *vmsd;

9
qemu/qom/cpu.c
View file

@ -168,14 +168,6 @@ static bool cpu_common_has_work(CPUState *cs)
return false;
}
static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
{
/* If no extra check is required, QEMU watchpoint match can be considered
* as an architectural match.
*/
return true;
}
ObjectClass *cpu_class_by_name(struct uc_struct *uc, const char *typename, const char *cpu_model)
{
CPUClass *cc = CPU_CLASS(uc, object_class_by_name(uc, typename));
@ -294,7 +286,6 @@ static void cpu_class_init(struct uc_struct *uc, ObjectClass *klass, void *data)
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->tcg_ops.debug_excp_handler = cpu_common_noop;
k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
k->tcg_ops.adjust_watchpoint_address = cpu_adjust_watchpoint_address;
k->tcg_ops.cpu_exec_enter = cpu_common_noop;
k->tcg_ops.cpu_exec_exit = cpu_common_noop;

4
qemu/target/arm/cpu.c
View file

@ -2112,12 +2112,12 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
cc->tcg_ops.debug_check_watchpoint = arm_debug_check_watchpoint;
#endif
#endif /* CONFIG_TCG */
}