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target-mips: add missing restriction in DAUI instruction

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rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Backports commit db77d8523909b32d798cd2c80de422b68f9e5c42 from qemu
This commit is contained in:
Leon Alrae 2018-02-15 16:21:55 -05:00 committed by Lioncash
parent 1a441096c0
commit 18dcbc7a64
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 1 deletions
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4
qemu/target-mips/translate.c
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@ -19676,7 +19676,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* OPC_DAUI */ /* OPC_DAUI */
check_mips_64(ctx); check_mips_64(ctx);
if (rt != 0) { if (rs == 0) {
generate_exception(ctx, EXCP_RI);
} else if (rt != 0) {
TCGv t0 = tcg_temp_new(tcg_ctx); TCGv t0 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t0, rs); gen_load_gpr(ctx, t0, rs);
tcg_gen_addi_tl(tcg_ctx, *cpu_gpr[rt], t0, imm << 16); tcg_gen_addi_tl(tcg_ctx, *cpu_gpr[rt], t0, imm << 16);