yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 23:05:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-mips: add missing restriction in DAUI instruction

Browse source 
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Backports commit db77d8523909b32d798cd2c80de422b68f9e5c42 from qemu
This commit is contained in:
Leon Alrae 2018-02-15 16:21:55 -05:00 committed by Lioncash
parent 1a441096c0
commit 18dcbc7a64
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
qemu/target-mips/translate.c
View file

@ -19676,7 +19676,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* OPC_DAUI */ /* OPC_DAUI */
check_mips_64(ctx); check_mips_64(ctx);
if (rt != 0) { if (rs == 0) {
generate_exception(ctx, EXCP_RI);
} else if (rt != 0) {
TCGv t0 = tcg_temp_new(tcg_ctx); TCGv t0 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t0, rs); gen_load_gpr(ctx, t0, rs);
tcg_gen_addi_tl(tcg_ctx, *cpu_gpr[rt], t0, imm << 16); tcg_gen_addi_tl(tcg_ctx, *cpu_gpr[rt], t0, imm << 16);