yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-07-08 01:30:41 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: Check undefined opcodes for SWP in A32 decoder

Browse source 
Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.

Backports commit c4869ca630a57f4269bb932ec7f719cef5bc79b8 from qemu
This commit is contained in:
Onur Sahin 2018-04-11 19:30:37 -04:00 committed by Lioncash
parent 87180dd231
commit 18e6b1549f
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
qemu/target/arm/translate.c
View file

@ -9417,11 +9417,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
} }
} }
tcg_temp_free_i32(tcg_ctx, addr); tcg_temp_free_i32(tcg_ctx, addr);
} else { } else if ((insn & 0x00300f00) == 0) {
/* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
* - SWP, SWPB
*/
TCGv taddr; TCGv taddr;
TCGMemOp opc = s->be_data; TCGMemOp opc = s->be_data;
/* SWP instruction */
rm = (insn) & 0xf; rm = (insn) & 0xf;
if (insn & (1 << 22)) { if (insn & (1 << 22)) {
@ -9439,6 +9442,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
get_mem_index(s), opc); get_mem_index(s), opc);
tcg_temp_free(tcg_ctx, taddr); tcg_temp_free(tcg_ctx, taddr);
store_reg(s, rd, tmp); store_reg(s, rd, tmp);
} else {
goto illegal_op;
} }
} }
} else { } else {