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target-arm: Add AArch64 access to PAR_EL1
Backports commit c96fc9b52d0a318d8026a0bcaba204d319ad91e0 from qemu
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@ -2658,6 +2658,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ "AT_S1E3W", 0,7,8, 1,6,1, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
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PL3_W, 0, NULL, 0, 0, {0, 0},
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NULL, NULL, ats_write64 },
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{ "PAR_EL1", 0,7,4, 3,0,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.par_el[1]), {0, 0},
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NULL, NULL, par_write },
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#endif
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/* TLB invalidate last level of translation table walk */
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{ "TLBIMVALIS", 15,8,3, 0,0,5, 0,
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