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https://github.com/yuzu-emu/unicorn.git
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target/arm: Convert float-to-integer VCVT insns to decodetree
Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Backports commit 3111bfc2da6ba0c8396dc97ca479942d711c6146 from qemu
This commit is contained in:
Peter Maydell
Lioncash
parent
f6c67559d4
commit
1a0d31c05e
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@ -2622,3 +2622,77 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
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tcg_temp_free_ptr(tcg_ctx, fpst);
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return true;
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}
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static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 vm;
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TCGv_ptr fpst;
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if (!vfp_access_check(s)) {
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return true;
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}
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fpst = get_fpstatus_ptr(s, false);
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vm = tcg_temp_new_i32(tcg_ctx);
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neon_load_reg32(s, vm, a->vm);
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if (a->s) {
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if (a->rz) {
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gen_helper_vfp_tosizs(tcg_ctx, vm, vm, fpst);
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} else {
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gen_helper_vfp_tosis(tcg_ctx, vm, vm, fpst);
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}
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} else {
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if (a->rz) {
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gen_helper_vfp_touizs(tcg_ctx, vm, vm, fpst);
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} else {
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gen_helper_vfp_touis(tcg_ctx, vm, vm, fpst);
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}
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}
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neon_store_reg32(s, vm, a->vd);
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tcg_temp_free_i32(tcg_ctx, vm);
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tcg_temp_free_ptr(tcg_ctx, fpst);
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return true;
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}
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static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 vd;
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TCGv_i64 vm;
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TCGv_ptr fpst;
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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fpst = get_fpstatus_ptr(s, false);
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vm = tcg_temp_new_i64(tcg_ctx);
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vd = tcg_temp_new_i32(tcg_ctx);
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neon_load_reg64(s, vm, a->vm);
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if (a->s) {
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if (a->rz) {
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gen_helper_vfp_tosizd(tcg_ctx, vd, vm, fpst);
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} else {
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gen_helper_vfp_tosid(tcg_ctx, vd, vm, fpst);
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}
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} else {
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if (a->rz) {
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gen_helper_vfp_touizd(tcg_ctx, vd, vm, fpst);
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} else {
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gen_helper_vfp_touid(tcg_ctx, vd, vm, fpst);
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}
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}
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neon_store_reg32(s, vd, a->vd);
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tcg_temp_free_i32(tcg_ctx, vd);
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tcg_temp_free_i64(tcg_ctx, vm);
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tcg_temp_free_ptr(tcg_ctx, fpst);
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return true;
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}
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@ -1477,9 +1477,7 @@ static inline void gen_vfp_##name(DisasContext *s, int dp, int neon) \
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tcg_temp_free_ptr(tcg_ctx, statusptr); \
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}
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VFP_GEN_FTOI(toui)
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VFP_GEN_FTOI(touiz)
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VFP_GEN_FTOI(tosi)
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VFP_GEN_FTOI(tosiz)
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#undef VFP_GEN_FTOI
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@ -1683,36 +1681,7 @@ static TCGv_ptr vfp_reg_ptr(DisasContext *s, bool dp, int reg)
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}
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#define tcg_gen_ld_f32 tcg_gen_ld_i32
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#define tcg_gen_ld_f64 tcg_gen_ld_i64
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#define tcg_gen_st_f32 tcg_gen_st_i32
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#define tcg_gen_st_f64 tcg_gen_st_i64
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static inline void gen_mov_F0_vreg(DisasContext *s, int dp, int reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (dp)
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tcg_gen_ld_f64(tcg_ctx, s->F0d, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
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else
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tcg_gen_ld_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
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}
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static inline void gen_mov_F1_vreg(DisasContext *s, int dp, int reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (dp)
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tcg_gen_ld_f64(tcg_ctx, s->F1d, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
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else
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tcg_gen_ld_f32(tcg_ctx, s->F1s, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
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}
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static inline void gen_mov_vreg_F0(DisasContext *s, int dp, int reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (dp)
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tcg_gen_st_f64(tcg_ctx, s->F0d, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
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else
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tcg_gen_st_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
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}
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#define ARM_CP_RW_BIT (1 << 20)
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@ -3077,9 +3046,6 @@ static void gen_neon_dup_high16(DisasContext *s, TCGv_i32 var)
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*/
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static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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{
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uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask;
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int dp, veclen;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
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return 1;
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}
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@ -3100,213 +3066,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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}
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}
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if (extract32(insn, 28, 4) == 0xf) {
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/*
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* Encodings with T=1 (Thumb) or unconditional (ARM): these
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* were all handled by the decodetree decoder, so any insn
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* patterns which get here must be UNDEF.
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*/
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return 1;
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}
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/*
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* FIXME: this access check should not take precedence over UNDEF
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* for invalid encodings; we will generate incorrect syndrome information
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* for attempts to execute invalid vfp/neon encodings with FP disabled.
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*/
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if (!vfp_access_check(s)) {
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return 0;
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}
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dp = ((insn & 0xf00) == 0xb00);
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switch ((insn >> 24) & 0xf) {
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case 0xe:
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if (insn & (1 << 4)) {
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/* already handled by decodetree */
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return 1;
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} else {
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/* data processing */
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bool rd_is_dp = dp;
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bool rm_is_dp = dp;
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bool no_output = false;
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/* The opcode is in bits 23, 21, 20 and 6. */
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op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
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rn = VFP_SREG_N(insn);
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switch (op) {
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case 0 ... 14:
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/* Already handled by decodetree */
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return 1;
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case 15:
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switch (rn) {
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case 0 ... 23:
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case 28 ... 31:
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/* Already handled by decodetree */
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return 1;
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default:
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break;
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}
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default:
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break;
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}
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if (op == 15) {
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/* rn is opcode, encoded as per VFP_SREG_N. */
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switch (rn) {
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case 0x18: /* vcvtr.u32.fxx */
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case 0x19: /* vcvtz.u32.fxx */
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case 0x1a: /* vcvtr.s32.fxx */
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case 0x1b: /* vcvtz.s32.fxx */
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rd_is_dp = false;
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break;
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default:
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return 1;
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}
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} else if (dp) {
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/* rn is register number */
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VFP_DREG_N(rn, insn);
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}
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if (rd_is_dp) {
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VFP_DREG_D(rd, insn);
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} else {
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rd = VFP_SREG_D(insn);
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}
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if (rm_is_dp) {
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VFP_DREG_M(rm, insn);
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} else {
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rm = VFP_SREG_M(insn);
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}
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veclen = s->vec_len;
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if (op == 15 && rn > 3) {
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veclen = 0;
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}
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/* Shut up compiler warnings. */
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delta_m = 0;
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delta_d = 0;
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bank_mask = 0;
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if (veclen > 0) {
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if (dp)
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bank_mask = 0xc;
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else
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bank_mask = 0x18;
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/* Figure out what type of vector operation this is. */
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if ((rd & bank_mask) == 0) {
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/* scalar */
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veclen = 0;
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} else {
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if (dp)
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delta_d = (s->vec_stride >> 1) + 1;
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else
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delta_d = s->vec_stride + 1;
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if ((rm & bank_mask) == 0) {
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/* mixed scalar/vector */
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delta_m = 0;
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} else {
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/* vector */
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delta_m = delta_d;
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}
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}
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}
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/* Load the initial operands. */
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if (op == 15) {
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switch (rn) {
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default:
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/* One source operand. */
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gen_mov_F0_vreg(s, rm_is_dp, rm);
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break;
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}
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} else {
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/* Two source operands. */
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gen_mov_F0_vreg(s, dp, rn);
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gen_mov_F1_vreg(s, dp, rm);
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}
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for (;;) {
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/* Perform the calculation. */
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switch (op) {
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case 15: /* extension space */
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switch (rn) {
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case 24: /* ftoui */
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gen_vfp_toui(s, dp, 0);
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break;
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case 25: /* ftouiz */
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gen_vfp_touiz(s, dp, 0);
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break;
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case 26: /* ftosi */
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gen_vfp_tosi(s, dp, 0);
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break;
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case 27: /* ftosiz */
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gen_vfp_tosiz(s, dp, 0);
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break;
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default: /* undefined */
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g_assert_not_reached();
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}
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break;
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default: /* undefined */
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return 1;
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}
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/* Write back the result, if any. */
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if (!no_output) {
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gen_mov_vreg_F0(s, rd_is_dp, rd);
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}
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/* break out of the loop if we have finished */
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if (veclen == 0) {
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break;
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}
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if (op == 15 && delta_m == 0) {
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/* single source one-many */
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while (veclen--) {
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rd = ((rd + delta_d) & (bank_mask - 1))
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| (rd & bank_mask);
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gen_mov_vreg_F0(s, dp, rd);
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}
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break;
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}
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/* Setup the next operands. */
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veclen--;
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rd = ((rd + delta_d) & (bank_mask - 1))
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| (rd & bank_mask);
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if (op == 15) {
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/* One source operand. */
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rm = ((rm + delta_m) & (bank_mask - 1))
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| (rm & bank_mask);
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gen_mov_F0_vreg(s, dp, rm);
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} else {
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/* Two source operands. */
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rn = ((rn + delta_d) & (bank_mask - 1))
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| (rn & bank_mask);
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gen_mov_F0_vreg(s, dp, rn);
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if (delta_m) {
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rm = ((rm + delta_m) & (bank_mask - 1))
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| (rm & bank_mask);
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gen_mov_F1_vreg(s, dp, rm);
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}
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}
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}
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}
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break;
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case 0xc:
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case 0xd:
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/* Already handled by decodetree */
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return 1;
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default:
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/* Should never happen. */
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return 1;
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}
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return 0;
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/* If the decodetree decoder didn't handle this insn, it must be UNDEF */
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return 1;
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}
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static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
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@ -234,3 +234,9 @@ VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \
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vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
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VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \
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vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
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# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size
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VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
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vd=%vd_sp vm=%vm_dp
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