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target/arm: Add isar tests for mte
Backports commit c7fd0baac0c24defec66263799faa8618327b352 from qemu
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@ -2220,7 +2220,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
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* migration or KVM state synchronization. (Typically this is for "registers"
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* migration or KVM state synchronization. (Typically this is for "registers"
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* which are actually used as instructions for cache maintenance and so on.)
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* which are actually used as instructions for cache maintenance and so on.)
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* IO indicates that this register does I/O and therefore its accesses
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* IO indicates that this register does I/O and therefore its accesses
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* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
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* need to be marked with gen_io_start() and also end the TB. In particular,
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* registers which implement clocks or timers require this.
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* registers which implement clocks or timers require this.
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* RAISES_EXC is for when the read or write hook might raise an exception;
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* RAISES_EXC is for when the read or write hook might raise an exception;
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* the generated code will synchronize the CPU state before calling the hook
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* the generated code will synchronize the CPU state before calling the hook
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@ -3671,6 +3671,16 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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}
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}
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static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
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}
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static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
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}
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static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
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{
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{
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return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
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return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
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