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target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01]
This is part of a reorganization to the set of mmu_idx. This emphasizes that they apply to the Secure EL1&0 regime. Backports commit fba37aedecb82506c62a1f9e81d066b4fd04e443 from qemu
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31837384b3
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@ -2804,8 +2804,8 @@ typedef enum ARMMMUIdx {
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ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
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ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
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ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
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ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
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ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
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ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A,
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ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A,
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ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
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ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
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ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
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@ -2830,8 +2830,8 @@ typedef enum ARMMMUIdxBit {
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ARMMMUIdxBit_E10_1 = 1 << 1,
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ARMMMUIdxBit_S1E2 = 1 << 2,
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ARMMMUIdxBit_S1E3 = 1 << 3,
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ARMMMUIdxBit_S1SE0 = 1 << 4,
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ARMMMUIdxBit_S1SE1 = 1 << 5,
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ARMMMUIdxBit_SE10_0 = 1 << 4,
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ARMMMUIdxBit_SE10_1 = 1 << 5,
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ARMMMUIdxBit_Stage2 = 1 << 6,
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ARMMMUIdxBit_MUser = 1 << 0,
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ARMMMUIdxBit_MPriv = 1 << 1,
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@ -2969,7 +2969,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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mmu_idx = ARMMMUIdx_Stage1_E1;
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break;
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case 1:
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mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
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mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
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break;
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default:
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g_assert_not_reached();
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@ -2979,13 +2979,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
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switch (el) {
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case 3:
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mmu_idx = ARMMMUIdx_S1SE0;
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mmu_idx = ARMMMUIdx_SE10_0;
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break;
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case 2:
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mmu_idx = ARMMMUIdx_Stage1_E0;
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break;
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case 1:
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mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
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mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
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break;
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default:
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g_assert_not_reached();
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@ -3039,7 +3039,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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case 0:
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switch (ri->opc1) {
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case 0: /* AT S1E1R, AT S1E1W */
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mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
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mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
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break;
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case 4: /* AT S1E2R, AT S1E2W */
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mmu_idx = ARMMMUIdx_S1E2;
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@ -3052,13 +3052,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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break;
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case 2: /* AT S1E0R, AT S1E0W */
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mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
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mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
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break;
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case 4: /* AT S12E1R, AT S12E1W */
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mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
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mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
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break;
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case 6: /* AT S12E0R, AT S12E0W */
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mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_E10_0;
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mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
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break;
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default:
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g_assert_not_reached();
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@ -3721,7 +3721,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
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static int vae1_tlbmask(CPUARMState *env)
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{
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
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return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
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} else {
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return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
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}
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@ -3762,7 +3762,7 @@ static int alle1_tlbmask(CPUARMState *env)
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*/
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
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return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
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} else if (arm_feature(env, ARM_FEATURE_EL2)) {
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return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2;
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} else {
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@ -8556,9 +8556,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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return 2;
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case ARMMMUIdx_S1E3:
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return 3;
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case ARMMMUIdx_S1SE0:
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case ARMMMUIdx_SE10_0:
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return arm_el_is_aa64(env, 3) ? 1 : 3;
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case ARMMMUIdx_S1SE1:
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case ARMMMUIdx_SE10_1:
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case ARMMMUIdx_Stage1_E0:
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case ARMMMUIdx_Stage1_E1:
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case ARMMMUIdx_MPrivNegPri:
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@ -8701,7 +8701,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
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static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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switch (mmu_idx) {
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case ARMMMUIdx_S1SE0:
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case ARMMMUIdx_SE10_0:
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case ARMMMUIdx_Stage1_E0:
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case ARMMMUIdx_MUser:
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case ARMMMUIdx_MSUser:
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@ -11170,7 +11170,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
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el = arm_current_el(env);
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if (el < 2 && arm_is_secure_below_el3(env)) {
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return ARMMMUIdx_S1SE0 + el;
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return ARMMMUIdx_SE10_0 + el;
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} else {
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return ARMMMUIdx_E10_0 + el;
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}
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@ -822,8 +822,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
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case ARMMMUIdx_MUser:
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return false;
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case ARMMMUIdx_S1E3:
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case ARMMMUIdx_S1SE0:
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case ARMMMUIdx_S1SE1:
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case ARMMMUIdx_SE10_0:
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case ARMMMUIdx_SE10_1:
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case ARMMMUIdx_MSPrivNegPri:
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case ARMMMUIdx_MSUserNegPri:
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case ARMMMUIdx_MSPriv:
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@ -117,8 +117,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)
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case ARMMMUIdx_E10_1:
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useridx = ARMMMUIdx_E10_0;
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break;
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case ARMMMUIdx_S1SE1:
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useridx = ARMMMUIdx_S1SE0;
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case ARMMMUIdx_SE10_1:
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useridx = ARMMMUIdx_SE10_0;
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break;
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case ARMMMUIdx_Stage2:
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g_assert_not_reached();
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@ -151,9 +151,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)
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case ARMMMUIdx_E10_1:
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return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
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case ARMMMUIdx_S1E3:
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case ARMMMUIdx_S1SE0:
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case ARMMMUIdx_S1SE1:
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return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
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case ARMMMUIdx_SE10_0:
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case ARMMMUIdx_SE10_1:
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return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
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case ARMMMUIdx_MUser:
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case ARMMMUIdx_MPriv:
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return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
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@ -128,7 +128,7 @@ static inline int default_exception_el(DisasContext *s)
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* exceptions can only be routed to ELs above 1, so we target the higher of
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* 1 or the current EL.
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*/
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return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
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return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
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? 3 : MAX(1, s->current_el);
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}
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