mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-03-23 06:25:12 +00:00
target/arm: Move some system registers into a substructure
Create struct ARMISARegisters, to be accessed during translation. Backports commit 47576b94af5c406fc6521fb336fb5c12beeac3f8 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
7087f7f398
commit
1a714e97af
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@ -136,9 +136,9 @@ static void arm_cpu_reset(CPUState *s)
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
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g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
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env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
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cpu->powered_off = cpu->start_powered_off;
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s->halted = cpu->start_powered_off;
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@ -684,7 +684,7 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
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*/
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cpu->id_pfr1 &= ~0xf0;
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cpu->id_aa64pfr0 &= ~0xf000;
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cpu->isar.id_aa64pfr0 &= ~0xf000;
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}
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if (!cpu->has_el2) {
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@ -701,7 +701,7 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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* registers if we don't have EL2. These are id_pfr1[15:12] and
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* id_aa64pfr0_el1[11:8].
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*/
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cpu->id_aa64pfr0 &= ~0xf00;
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cpu->isar.id_aa64pfr0 &= ~0xf00;
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cpu->id_pfr1 &= ~0xf000;
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}
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@ -903,8 +903,8 @@ static void arm1136_r2_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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@ -914,11 +914,11 @@ static void arm1136_r2_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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}
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@ -935,8 +935,8 @@ static void arm1136_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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cpu->midr = 0x4117b363;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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@ -946,11 +946,11 @@ static void arm1136_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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}
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@ -968,8 +968,8 @@ static void arm1176_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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cpu->midr = 0x410fb767;
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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@ -979,11 +979,11 @@ static void arm1176_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->id_isar0 = 0x0140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231121;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x01141;
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cpu->isar.id_isar0 = 0x0140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231121;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x01141;
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cpu->reset_auxcr = 7;
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}
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@ -999,8 +999,8 @@ static void arm11mpcore_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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cpu->midr = 0x410fb022;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->isar.mvfr0 = 0x11111111;
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cpu->isar.mvfr1 = 0x00000000;
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cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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@ -1009,11 +1009,11 @@ static void arm11mpcore_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
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cpu->id_isar0 = 0x00100011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11221011;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->isar.id_isar0 = 0x00100011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11221011;
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cpu->isar.id_isar3 = 0x01102131;
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cpu->isar.id_isar4 = 0x141;
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cpu->reset_auxcr = 1;
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}
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@ -1042,13 +1042,13 @@ static void cortex_m3_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->id_isar0 = 0x01141110;
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cpu->id_isar1 = 0x02111000;
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cpu->id_isar2 = 0x21112231;
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cpu->id_isar3 = 0x01111110;
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cpu->id_isar4 = 0x01310102;
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cpu->id_isar5 = 0x00000000;
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cpu->id_isar6 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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@ -1069,13 +1069,13 @@ static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->id_isar0 = 0x01141110;
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cpu->id_isar1 = 0x02111000;
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cpu->id_isar2 = 0x21112231;
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cpu->id_isar3 = 0x01111110;
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cpu->id_isar4 = 0x01310102;
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cpu->id_isar5 = 0x00000000;
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cpu->id_isar6 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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@ -1098,13 +1098,13 @@ static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->id_isar0 = 0x01101110;
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cpu->id_isar1 = 0x02212000;
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cpu->id_isar2 = 0x20232232;
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cpu->id_isar3 = 0x01111131;
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cpu->id_isar4 = 0x01310132;
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cpu->id_isar5 = 0x00000000;
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cpu->id_isar6 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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cpu->isar.id_isar3 = 0x01111131;
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cpu->isar.id_isar4 = 0x01310132;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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cpu->clidr = 0x00000000;
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cpu->ctr = 0x8000c000;
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}
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@ -1146,13 +1146,13 @@ static void cortex_r5_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01200000;
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cpu->id_mmfr3 = 0x0211;
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cpu->id_isar0 = 0x02101111;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232141;
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cpu->id_isar3 = 0x01112131;
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cpu->id_isar4 = 0x0010142;
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cpu->id_isar5 = 0x0;
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cpu->id_isar6 = 0x0;
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cpu->isar.id_isar0 = 0x02101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232141;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x0010142;
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cpu->isar.id_isar5 = 0x0;
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cpu->isar.id_isar6 = 0x0;
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cpu->mp_is_up = true;
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define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
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}
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@ -1186,8 +1186,8 @@ static void cortex_a8_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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cpu->midr = 0x410fc080;
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cpu->reset_fpsid = 0x410330c0;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x00011111;
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cpu->isar.mvfr0 = 0x11110222;
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cpu->isar.mvfr1 = 0x00011111;
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cpu->ctr = 0x82048004;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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@ -1198,11 +1198,11 @@ static void cortex_a8_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01202000;
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cpu->id_mmfr3 = 0x11;
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cpu->id_isar0 = 0x00101111;
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cpu->id_isar1 = 0x12112111;
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cpu->id_isar2 = 0x21232031;
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cpu->id_isar3 = 0x11112131;
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cpu->id_isar4 = 0x00111142;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x12112111;
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cpu->isar.id_isar2 = 0x21232031;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x00111142;
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cpu->dbgdidr = 0x15141000;
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cpu->clidr = (1 << 27) | (2 << 24) | 3;
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cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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@ -1257,8 +1257,8 @@ static void cortex_a9_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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set_feature(&cpu->env, ARM_FEATURE_CBAR);
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cpu->midr = 0x410fc090;
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cpu->reset_fpsid = 0x41033090;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x01111111;
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cpu->isar.mvfr0 = 0x11110222;
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cpu->isar.mvfr1 = 0x01111111;
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cpu->ctr = 0x80038003;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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@ -1269,11 +1269,11 @@ static void cortex_a9_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01230000;
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cpu->id_mmfr3 = 0x00002111;
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cpu->id_isar0 = 0x00101111;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232041;
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cpu->id_isar3 = 0x11112131;
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cpu->id_isar4 = 0x00111142;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x00111142;
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cpu->dbgdidr = 0x35141000;
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cpu->clidr = (1 << 27) | (1 << 24) | 3;
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cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
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@ -1318,8 +1318,8 @@ static void cortex_a7_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
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cpu->midr = 0x410fc075;
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cpu->reset_fpsid = 0x41023075;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x11111111;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x11111111;
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cpu->ctr = 0x84448003;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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@ -1335,11 +1335,11 @@ static void cortex_a7_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
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* table 4-41 gives 0x02101110, which includes the arm div insns.
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*/
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cpu->id_isar0 = 0x02101110;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232041;
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cpu->id_isar3 = 0x11112131;
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cpu->id_isar4 = 0x10011142;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x10011142;
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cpu->dbgdidr = 0x3515f005;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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@ -1364,8 +1364,8 @@ static void cortex_a15_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
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cpu->midr = 0x412fc0f1;
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cpu->reset_fpsid = 0x410430f0;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x11111111;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x11111111;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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@ -1378,11 +1378,11 @@ static void cortex_a15_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->id_mmfr1 = 0x20000000;
|
||||
cpu->id_mmfr2 = 0x01240000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232041;
|
||||
cpu->id_isar3 = 0x11112131;
|
||||
cpu->id_isar4 = 0x10011142;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232041;
|
||||
cpu->isar.id_isar3 = 0x11112131;
|
||||
cpu->isar.id_isar4 = 0x10011142;
|
||||
cpu->dbgdidr = 0x3515f021;
|
||||
cpu->clidr = 0x0a200023;
|
||||
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
|
||||
|
|
|
|||
|
|
@ -773,13 +773,28 @@ typedef struct ARMCPU {
|
|||
* ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
|
||||
* is used for reset values of non-constant registers; no reset_
|
||||
* prefix means a constant register.
|
||||
* Some of these registers are split out into a substructure that
|
||||
* is shared with the translators to control the ISA.
|
||||
*/
|
||||
struct ARMISARegisters {
|
||||
uint32_t id_isar0;
|
||||
uint32_t id_isar1;
|
||||
uint32_t id_isar2;
|
||||
uint32_t id_isar3;
|
||||
uint32_t id_isar4;
|
||||
uint32_t id_isar5;
|
||||
uint32_t id_isar6;
|
||||
uint32_t mvfr0;
|
||||
uint32_t mvfr1;
|
||||
uint32_t mvfr2;
|
||||
uint64_t id_aa64isar0;
|
||||
uint64_t id_aa64isar1;
|
||||
uint64_t id_aa64pfr0;
|
||||
uint64_t id_aa64pfr1;
|
||||
} isar;
|
||||
uint32_t midr;
|
||||
uint32_t revidr;
|
||||
uint32_t reset_fpsid;
|
||||
uint32_t mvfr0;
|
||||
uint32_t mvfr1;
|
||||
uint32_t mvfr2;
|
||||
uint32_t ctr;
|
||||
uint32_t reset_sctlr;
|
||||
uint32_t id_pfr0;
|
||||
|
|
@ -793,21 +808,10 @@ typedef struct ARMCPU {
|
|||
uint32_t id_mmfr2;
|
||||
uint32_t id_mmfr3;
|
||||
uint32_t id_mmfr4;
|
||||
uint32_t id_isar0;
|
||||
uint32_t id_isar1;
|
||||
uint32_t id_isar2;
|
||||
uint32_t id_isar3;
|
||||
uint32_t id_isar4;
|
||||
uint32_t id_isar5;
|
||||
uint32_t id_isar6;
|
||||
uint64_t id_aa64pfr0;
|
||||
uint64_t id_aa64pfr1;
|
||||
uint64_t id_aa64dfr0;
|
||||
uint64_t id_aa64dfr1;
|
||||
uint64_t id_aa64afr0;
|
||||
uint64_t id_aa64afr1;
|
||||
uint64_t id_aa64isar0;
|
||||
uint64_t id_aa64isar1;
|
||||
uint64_t id_aa64mmfr0;
|
||||
uint64_t id_aa64mmfr1;
|
||||
uint32_t dbgdidr;
|
||||
|
|
|
|||
|
|
@ -101,9 +101,9 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->midr = 0x411fd070;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034070;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x12111111;
|
||||
cpu->mvfr2 = 0x00000043;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->id_pfr0 = 0x00000131;
|
||||
|
|
@ -114,18 +114,18 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->id_mmfr1 = 0x40000000;
|
||||
cpu->id_mmfr2 = 0x01260000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232042;
|
||||
cpu->id_isar3 = 0x01112131;
|
||||
cpu->id_isar4 = 0x00011142;
|
||||
cpu->id_isar5 = 0x00011121;
|
||||
cpu->id_isar6 = 0;
|
||||
cpu->id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_isar6 = 0;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->id_aa64dfr0 = 0x10305106;
|
||||
cpu->pmceid0 = 0x00000000;
|
||||
cpu->pmceid1 = 0x00000000;
|
||||
cpu->id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->id_aa64mmfr0 = 0x00001124;
|
||||
cpu->dbgdidr = 0x3516d000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
|
|
@ -159,9 +159,9 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->midr = 0x410fd034;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034070;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x12111111;
|
||||
cpu->mvfr2 = 0x00000043;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->id_pfr0 = 0x00000131;
|
||||
|
|
@ -172,16 +172,16 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->id_mmfr1 = 0x40000000;
|
||||
cpu->id_mmfr2 = 0x01260000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232042;
|
||||
cpu->id_isar3 = 0x01112131;
|
||||
cpu->id_isar4 = 0x00011142;
|
||||
cpu->id_isar5 = 0x00011121;
|
||||
cpu->id_isar6 = 0;
|
||||
cpu->id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_isar6 = 0;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->id_aa64dfr0 = 0x10305106;
|
||||
cpu->id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
|
||||
cpu->dbgdidr = 0x3516d000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
|
|
@ -214,9 +214,9 @@ static void aarch64_a72_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->midr = 0x410fd083;
|
||||
cpu->revidr = 0x00000000;
|
||||
cpu->reset_fpsid = 0x41034080;
|
||||
cpu->mvfr0 = 0x10110222;
|
||||
cpu->mvfr1 = 0x12111111;
|
||||
cpu->mvfr2 = 0x00000043;
|
||||
cpu->isar.mvfr0 = 0x10110222;
|
||||
cpu->isar.mvfr1 = 0x12111111;
|
||||
cpu->isar.mvfr2 = 0x00000043;
|
||||
cpu->ctr = 0x8444c004;
|
||||
cpu->reset_sctlr = 0x00c50838;
|
||||
cpu->id_pfr0 = 0x00000131;
|
||||
|
|
@ -227,17 +227,17 @@ static void aarch64_a72_initfn(struct uc_struct *uc, Object *obj, void *opaque)
|
|||
cpu->id_mmfr1 = 0x40000000;
|
||||
cpu->id_mmfr2 = 0x01260000;
|
||||
cpu->id_mmfr3 = 0x02102211;
|
||||
cpu->id_isar0 = 0x02101110;
|
||||
cpu->id_isar1 = 0x13112111;
|
||||
cpu->id_isar2 = 0x21232042;
|
||||
cpu->id_isar3 = 0x01112131;
|
||||
cpu->id_isar4 = 0x00011142;
|
||||
cpu->id_isar5 = 0x00011121;
|
||||
cpu->id_aa64pfr0 = 0x00002222;
|
||||
cpu->isar.id_isar0 = 0x02101110;
|
||||
cpu->isar.id_isar1 = 0x13112111;
|
||||
cpu->isar.id_isar2 = 0x21232042;
|
||||
cpu->isar.id_isar3 = 0x01112131;
|
||||
cpu->isar.id_isar4 = 0x00011142;
|
||||
cpu->isar.id_isar5 = 0x00011121;
|
||||
cpu->isar.id_aa64pfr0 = 0x00002222;
|
||||
cpu->id_aa64dfr0 = 0x10305106;
|
||||
cpu->pmceid0 = 0x00000000;
|
||||
cpu->pmceid1 = 0x00000000;
|
||||
cpu->id_aa64isar0 = 0x00011120;
|
||||
cpu->isar.id_aa64isar0 = 0x00011120;
|
||||
cpu->id_aa64mmfr0 = 0x00001124;
|
||||
cpu->dbgdidr = 0x3516d000;
|
||||
cpu->clidr = 0x0a200023;
|
||||
|
|
|
|||
|
|
@ -4281,7 +4281,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
|||
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
|
||||
{
|
||||
ARMCPU *cpu = arm_env_get_cpu(env);
|
||||
uint64_t pfr0 = cpu->id_aa64pfr0;
|
||||
uint64_t pfr0 = cpu->isar.id_aa64pfr0;
|
||||
|
||||
if (env->gicv3state) {
|
||||
pfr0 |= 1 << 24;
|
||||
|
|
@ -4330,21 +4330,21 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ "ID_MMFR3", 0,0,1, 3,0,7, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_mmfr3 },
|
||||
{ "ID_ISAR0", 0,0,2, 3,0,0, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar0 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar0 },
|
||||
{ "ID_ISAR1", 0,0,2, 3,0,1, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar1 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar1 },
|
||||
{ "ID_ISAR2", 0,0,2, 3,0,2, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar2 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar2 },
|
||||
{ "ID_ISAR3", 0,0,2, 3,0,3, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar3 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar3 },
|
||||
{ "ID_ISAR4", 0,0,2, 3,0,4, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar4 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar4 },
|
||||
{ "ID_ISAR5", 0,0,2, 3,0,5, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar5 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar5 },
|
||||
{ "ID_MMFR4", 0,0,2, 3,0,6, ARM_CP_STATE_BOTH, ARM_CP_CONST,
|
||||
PL1_R, 0, NULL, cpu->id_mmfr4 },
|
||||
{ "ID_ISAR6", 0,0,2, 3,0,7, ARM_CP_STATE_BOTH,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar6 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_isar6 },
|
||||
REGINFO_SENTINEL
|
||||
};
|
||||
define_arm_cp_regs(cpu, v6_idregs);
|
||||
|
|
@ -4403,7 +4403,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->id_aa64pfr0, 0, {0, 0},
|
||||
NULL, id_aa64pfr0_read, arm_cp_write_ignore },
|
||||
{ "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64pfr1},
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64pfr1},
|
||||
{ "ID_AA64PFR2_EL1_RESERVED", 0,0,4, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
PL1_R, 0, NULL, 0 },
|
||||
{ "ID_AA64PFR3_EL1_RESERVED", 0,0,4, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
|
|
@ -4434,9 +4434,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ "ID_AA64AFR3_EL1_RESERVED", 0,0,5, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
PL1_R, 0, NULL, 0 },
|
||||
{ "ID_AA64ISAR0_EL1", 0,0,6, 3,0,0, ARM_CP_STATE_AA64,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64isar0 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64isar0 },
|
||||
{ "ID_AA64ISAR1_EL1", 0,0,6, 3,0,1, ARM_CP_STATE_AA64,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64isar1 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64isar1 },
|
||||
{ "ID_AA64ISAR2_EL1_RESERVED", 0,0,6, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
PL1_R, 0, NULL, 0 },
|
||||
{ "ID_AA64ISAR3_EL1_RESERVED", 0,0,6, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
|
|
@ -4466,11 +4466,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
{ "ID_AA64MMFR7_EL1_RESERVED", 0,0,7, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
PL1_R, 0, NULL, 0 },
|
||||
{ "MVFR0_EL1", 0,0,3, 3,0,0, ARM_CP_STATE_AA64,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr0 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.mvfr0 },
|
||||
{ "MVFR1_EL1", 0,0,3, 3,0,1, ARM_CP_STATE_AA64,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr1 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.mvfr1 },
|
||||
{ "MVFR2_EL1", 0,0,3, 3,0,2, ARM_CP_STATE_AA64,
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr2 },
|
||||
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.mvfr2 },
|
||||
{ "MVFR3_EL1_RESERVED", 0,0,3, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
PL1_R, 0, NULL, 0 },
|
||||
{ "MVFR4_EL1_RESERVED", 0,0,3, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
|
||||
|
|
|
|||
Loading…
Reference in a new issue