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target/arm: Implement ARMv8M's PMSAv8 registers

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As part of ARMv8M, we need to add support for the PMSAv8 MPU
architecture.

PMSAv8 differs from PMSAv7 both in register/data layout (for instance
using base and limit registers rather than base and size) and also in
behaviour (for example it does not have subregions); rather than
trying to wedge it into the existing PMSAv7 code and data structures,
we define separate ones.

This commit adds the data structures which hold the state for a
PMSAv8 MPU and the register interface to it. The implementation of
the MPU behaviour will be added in a subsequent commit.

Backports commit 0e1a46bbd2d6c39614b87f4e88ea305acce8a35f from qemu
This commit is contained in:
Peter Maydell 2018-03-04 20:45:39 -05:00 committed by Lioncash
parent 6d2bcf6ed8
commit 1acd9efdc2
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 38 additions and 11 deletions
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36
qemu/target/arm/cpu.c
View file

@ -231,17 +231,25 @@ static void arm_cpu_reset(CPUState *s)
env->vfp.xregs[ARM_VFP_FPEXC] = 0; env->vfp.xregs[ARM_VFP_FPEXC] = 0;
#endif #endif
if (arm_feature(env, ARM_FEATURE_PMSA) && if (arm_feature(env, ARM_FEATURE_PMSA)) {
arm_feature(env, ARM_FEATURE_V7)) {
if (cpu->pmsav7_dregion > 0) { if (cpu->pmsav7_dregion > 0) {
memset(env->pmsav7.drbar, 0, if (arm_feature(env, ARM_FEATURE_V8)) {
sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); memset(env->pmsav8.rbar, 0,
memset(env->pmsav7.drsr, 0, sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion);
sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); memset(env->pmsav8.rlar, 0,
memset(env->pmsav7.dracr, 0, sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion);
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } else if (arm_feature(env, ARM_FEATURE_V7)) {
memset(env->pmsav7.drbar, 0,
sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
memset(env->pmsav7.drsr, 0,
sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
memset(env->pmsav7.dracr, 0,
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
}
} }
env->pmsav7.rnr = 0; env->pmsav7.rnr = 0;
env->pmsav8.mair0 = 0;
env->pmsav8.mair1 = 0;
} }
set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_to_zero(1, &env->vfp.standard_fp_status);
@ -603,9 +611,15 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
} }
if (nr) { if (nr) {
env->pmsav7.drbar = g_new0(uint32_t, nr); if (arm_feature(env, ARM_FEATURE_V8)) {
env->pmsav7.drsr = g_new0(uint32_t, nr); /* PMSAv8 */
env->pmsav7.dracr = g_new0(uint32_t, nr); env->pmsav8.rbar = g_new0(uint32_t, nr);
env->pmsav8.rlar = g_new0(uint32_t, nr);
} else {
env->pmsav7.drbar = g_new0(uint32_t, nr);
env->pmsav7.drsr = g_new0(uint32_t, nr);
env->pmsav7.dracr = g_new0(uint32_t, nr);
}
} }
} }

13
qemu/target/arm/cpu.h
View file

@ -529,6 +529,19 @@ typedef struct CPUARMState {
uint32_t rnr; uint32_t rnr;
} pmsav7; } pmsav7;
/* PMSAv8 MPU */
struct {
/* The PMSAv8 implementation also shares some PMSAv7 config
* and state:
* pmsav7.rnr (region number register)
* pmsav7_dregion (number of configured regions)
*/
uint32_t *rbar;
uint32_t *rlar;
uint32_t mair0;
uint32_t mair1;
} pmsav8;
void *nvic; void *nvic;
const struct arm_boot_info *boot_info; const struct arm_boot_info *boot_info;