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i386: Initialize cache information for EPYC family processors

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Initialize pre-determined cache information for EPYC processors.

Backports commit fe52acd2a054b97765963a42037f2f886545e30c from qemu
This commit is contained in:
Babu Moger 2018-05-17 18:59:36 -04:00 committed by Lioncash
parent c5b8a6a704
commit 1add2da704
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 55 additions and 0 deletions
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55
qemu/target/i386/cpu.c
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@ -1242,6 +1242,57 @@ struct X86CPUDefinition {
CPUCaches *cache_info;
};
static CPUCaches epyc_cache_info = {
{
DCACHE,
1,
32 * KiB,
64,
8,
1,
64,
1,
1,
true,
},
{
ICACHE,
1,
64 * KiB,
64,
4,
1,
256,
1,
1,
true,
},
{
UNIFIED_CACHE,
2,
512 * KiB,
64,
8,
1,
1024,
1,
},
{
UNIFIED_CACHE,
3,
8 * MiB,
64,
16,
1,
8192,
1,
true,
false,
true,
true,
},
};
static X86CPUDefinition builtin_x86_defs[] = {
{
"qemu64",
@ -2983,6 +3034,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
},
"AMD EPYC Processor",
false,
&epyc_cache_info,
},
{
"EPYC-IBPB",
@ -3048,6 +3101,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
},
"AMD EPYC Processor (with IBPB)",
false,
&epyc_cache_info,
},
};