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target/arm: Update WHILE for PREDDESC

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Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.

Backports e610906c56f98c76888d45beb7f579935dd61a70
This commit is contained in:
Richard Henderson 2021-03-30 14:42:39 -04:00 committed by Lioncash
parent c374bdc9ca
commit 1b05fd82b7
2 changed files with 6 additions and 5 deletions
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4
qemu/target/arm/sve_helper.c
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@ -2849,8 +2849,8 @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
{ {
uintptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
uint64_t esz_mask = pred_esz_masks[esz]; uint64_t esz_mask = pred_esz_masks[esz];
ARMPredicateReg *d = vd; ARMPredicateReg *d = vd;
uint32_t flags; uint32_t flags;

7
qemu/target/arm/translate-sve.c
View file

@ -3200,7 +3200,8 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
TCGv_i64 op0, op1, t0, t1, tmax; TCGv_i64 op0, op1, t0, t1, tmax;
TCGv_i32 t2, t3; TCGv_i32 t2, t3;
TCGv_ptr ptr; TCGv_ptr ptr;
unsigned desc, vsz = vec_full_reg_size(s); unsigned vsz = vec_full_reg_size(s);
unsigned desc = 0;
TCGCond cond; TCGCond cond;
if (!sve_access_check(s)) { if (!sve_access_check(s)) {
@ -3264,8 +3265,8 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
/* Scale elements to bits. */ /* Scale elements to bits. */
tcg_gen_shli_i32(tcg_ctx, t2, t2, a->esz); tcg_gen_shli_i32(tcg_ctx, t2, t2, a->esz);
desc = (vsz / 8) - 2; desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8);
desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
t3 = tcg_const_i32(tcg_ctx, desc); t3 = tcg_const_i32(tcg_ctx, desc);
ptr = tcg_temp_new_ptr(tcg_ctx); ptr = tcg_temp_new_ptr(tcg_ctx);