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target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
For the A64 instruction set, the semihosting call instruction is 'HLT 0xf000'. Wire this up to call do_arm_semihosting() if semihosting is enabled. Backports commit 8012c84ff92a36d05dfe61af9b24dd01a7ea25e4 from qemu
This commit is contained in:
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f81894dddb
commit
1b88e0e8c8
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_aarch64
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#define scr_write scr_write_aarch64
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#define sctlr_write sctlr_write_aarch64
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#define semihosting_enabled semihosting_enabled_aarch64
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#define semihosting_get_target semihosting_get_target_aarch64
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#define semihosting_get_arg semihosting_get_arg_aarch64
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#define semihosting_get_argc semihosting_get_argc_aarch64
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_aarch64eb
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#define scr_write scr_write_aarch64eb
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#define sctlr_write sctlr_write_aarch64eb
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#define semihosting_enabled semihosting_enabled_aarch64eb
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#define semihosting_get_target semihosting_get_target_aarch64eb
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#define semihosting_get_arg semihosting_get_arg_aarch64eb
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#define semihosting_get_argc semihosting_get_argc_aarch64eb
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_arm
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#define scr_write scr_write_arm
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#define sctlr_write sctlr_write_arm
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#define semihosting_enabled semihosting_enabled_arm
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#define semihosting_get_target semihosting_get_target_arm
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#define semihosting_get_arg semihosting_get_arg_arm
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#define semihosting_get_argc semihosting_get_argc_arm
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_armeb
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#define scr_write scr_write_armeb
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#define sctlr_write sctlr_write_armeb
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#define semihosting_enabled semihosting_enabled_armeb
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#define semihosting_get_target semihosting_get_target_armeb
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#define semihosting_get_arg semihosting_get_arg_armeb
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#define semihosting_get_argc semihosting_get_argc_armeb
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@ -2588,11 +2588,6 @@ symbols = (
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'save_globals',
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'scr_write',
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'sctlr_write',
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'semihosting_enabled',
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'semihosting_get_target',
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'semihosting_get_arg',
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'semihosting_get_argc',
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'semihosting_get_cmdline',
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'set_bit',
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'set_bits',
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'set_default_nan_mode',
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_m68k
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#define scr_write scr_write_m68k
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#define sctlr_write sctlr_write_m68k
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#define semihosting_enabled semihosting_enabled_m68k
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#define semihosting_get_target semihosting_get_target_m68k
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#define semihosting_get_arg semihosting_get_arg_m68k
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#define semihosting_get_argc semihosting_get_argc_m68k
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_mips
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#define scr_write scr_write_mips
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#define sctlr_write sctlr_write_mips
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#define semihosting_enabled semihosting_enabled_mips
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#define semihosting_get_target semihosting_get_target_mips
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#define semihosting_get_arg semihosting_get_arg_mips
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#define semihosting_get_argc semihosting_get_argc_mips
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_mips64
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#define scr_write scr_write_mips64
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#define sctlr_write sctlr_write_mips64
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#define semihosting_enabled semihosting_enabled_mips64
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#define semihosting_get_target semihosting_get_target_mips64
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#define semihosting_get_arg semihosting_get_arg_mips64
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#define semihosting_get_argc semihosting_get_argc_mips64
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_mips64el
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#define scr_write scr_write_mips64el
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#define sctlr_write sctlr_write_mips64el
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#define semihosting_enabled semihosting_enabled_mips64el
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#define semihosting_get_target semihosting_get_target_mips64el
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#define semihosting_get_arg semihosting_get_arg_mips64el
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#define semihosting_get_argc semihosting_get_argc_mips64el
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_mipsel
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#define scr_write scr_write_mipsel
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#define sctlr_write sctlr_write_mipsel
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#define semihosting_enabled semihosting_enabled_mipsel
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#define semihosting_get_target semihosting_get_target_mipsel
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#define semihosting_get_arg semihosting_get_arg_mipsel
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#define semihosting_get_argc semihosting_get_argc_mipsel
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_powerpc
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#define scr_write scr_write_powerpc
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#define sctlr_write sctlr_write_powerpc
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#define semihosting_enabled semihosting_enabled_powerpc
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#define semihosting_get_target semihosting_get_target_powerpc
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#define semihosting_get_arg semihosting_get_arg_powerpc
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#define semihosting_get_argc semihosting_get_argc_powerpc
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_sparc
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#define scr_write scr_write_sparc
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#define sctlr_write sctlr_write_sparc
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#define semihosting_enabled semihosting_enabled_sparc
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#define semihosting_get_target semihosting_get_target_sparc
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#define semihosting_get_arg semihosting_get_arg_sparc
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#define semihosting_get_argc semihosting_get_argc_sparc
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_sparc64
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#define scr_write scr_write_sparc64
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#define sctlr_write sctlr_write_sparc64
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#define semihosting_enabled semihosting_enabled_sparc64
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#define semihosting_get_target semihosting_get_target_sparc64
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#define semihosting_get_arg semihosting_get_arg_sparc64
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#define semihosting_get_argc semihosting_get_argc_sparc64
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@ -58,6 +58,7 @@
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#define EXCP_SMC 13 /* Secure Monitor Call */
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#define EXCP_VIRQ 14
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#define EXCP_VFIQ 15
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#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
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#define ARMV7M_EXCP_RESET 1
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#define ARMV7M_EXCP_NMI 2
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@ -570,6 +570,13 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
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case EXCP_VFIQ:
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addr += 0x100;
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break;
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case EXCP_SEMIHOST:
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/* UNICORN: Commented out
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qemu_log_mask(CPU_LOG_INT,
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"...handling as semihosting call 0x%" PRIx64 "\n",
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env->xregs[0]);
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env->xregs[0] = do_arm_semihosting(env);*/
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return;
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default:
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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}
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@ -36,6 +36,7 @@ static inline bool excp_is_internal(int excp)
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|| excp == EXCP_HALTED
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|| excp == EXCP_EXCEPTION_EXIT
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|| excp == EXCP_KERNEL_TRAP
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|| excp == EXCP_SEMIHOST
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|| excp == EXCP_STREX;
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}
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@ -59,6 +60,7 @@ static const char * const excnames[] = {
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"Secure Monitor Call",
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"Virtual IRQ",
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"Virtual FIQ",
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"Semihosting call",
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};
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static inline void arm_log_exception(int idx)
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@ -1584,8 +1584,27 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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break;
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}
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/* HLT */
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unsupported_encoding(s, insn);
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/* HLT. This has two purposes.
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* Architecturally, it is an external halting debug instruction.
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* Since QEMU doesn't implement external debug, we treat this as
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* it is required for halting debug disabled: it will UNDEF.
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* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
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*/
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if (semihosting_enabled() && imm16 == 0xf000) {
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#ifndef CONFIG_USER_ONLY
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/* In system mode, don't allow userspace access to semihosting,
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* to provide some semblance of security (and for consistency
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* with our 32-bit semihosting).
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*/
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if (s->current_el == 0) {
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unsupported_encoding(s, insn);
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break;
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}
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#endif
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gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
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} else {
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unsupported_encoding(s, insn);
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}
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break;
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case 5:
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if (op2_ll < 1 || op2_ll > 3) {
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@ -2582,7 +2582,6 @@
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#define save_globals save_globals_x86_64
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#define scr_write scr_write_x86_64
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#define sctlr_write sctlr_write_x86_64
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#define semihosting_enabled semihosting_enabled_x86_64
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#define semihosting_get_target semihosting_get_target_x86_64
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#define semihosting_get_arg semihosting_get_arg_x86_64
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#define semihosting_get_argc semihosting_get_argc_x86_64
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