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target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction

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For the A64 instruction set, the semihosting call instruction
is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
if semihosting is enabled.

Backports commit 8012c84ff92a36d05dfe61af9b24dd01a7ea25e4 from qemu
This commit is contained in:
Peter Maydell 2018-02-15 10:53:48 -05:00 committed by Lioncash
parent f81894dddb
commit 1b88e0e8c8
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
18 changed files with 31 additions and 20 deletions
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1
qemu/aarch64.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_aarch64
#define scr_write scr_write_aarch64
#define sctlr_write sctlr_write_aarch64
#define semihosting_enabled semihosting_enabled_aarch64
#define semihosting_get_target semihosting_get_target_aarch64
#define semihosting_get_arg semihosting_get_arg_aarch64
#define semihosting_get_argc semihosting_get_argc_aarch64

1
qemu/aarch64eb.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_aarch64eb
#define scr_write scr_write_aarch64eb
#define sctlr_write sctlr_write_aarch64eb
#define semihosting_enabled semihosting_enabled_aarch64eb
#define semihosting_get_target semihosting_get_target_aarch64eb
#define semihosting_get_arg semihosting_get_arg_aarch64eb
#define semihosting_get_argc semihosting_get_argc_aarch64eb

1
qemu/arm.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_arm
#define scr_write scr_write_arm
#define sctlr_write sctlr_write_arm
#define semihosting_enabled semihosting_enabled_arm
#define semihosting_get_target semihosting_get_target_arm
#define semihosting_get_arg semihosting_get_arg_arm
#define semihosting_get_argc semihosting_get_argc_arm

1
qemu/armeb.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_armeb
#define scr_write scr_write_armeb
#define sctlr_write sctlr_write_armeb
#define semihosting_enabled semihosting_enabled_armeb
#define semihosting_get_target semihosting_get_target_armeb
#define semihosting_get_arg semihosting_get_arg_armeb
#define semihosting_get_argc semihosting_get_argc_armeb

5
qemu/header_gen.py
View file

@ -2588,11 +2588,6 @@ symbols = (
'save_globals',
'scr_write',
'sctlr_write',
'semihosting_enabled',
'semihosting_get_target',
'semihosting_get_arg',
'semihosting_get_argc',
'semihosting_get_cmdline',
'set_bit',
'set_bits',
'set_default_nan_mode',

1
qemu/m68k.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_m68k
#define scr_write scr_write_m68k
#define sctlr_write sctlr_write_m68k
#define semihosting_enabled semihosting_enabled_m68k
#define semihosting_get_target semihosting_get_target_m68k
#define semihosting_get_arg semihosting_get_arg_m68k
#define semihosting_get_argc semihosting_get_argc_m68k

1
qemu/mips.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_mips
#define scr_write scr_write_mips
#define sctlr_write sctlr_write_mips
#define semihosting_enabled semihosting_enabled_mips
#define semihosting_get_target semihosting_get_target_mips
#define semihosting_get_arg semihosting_get_arg_mips
#define semihosting_get_argc semihosting_get_argc_mips

1
qemu/mips64.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_mips64
#define scr_write scr_write_mips64
#define sctlr_write sctlr_write_mips64
#define semihosting_enabled semihosting_enabled_mips64
#define semihosting_get_target semihosting_get_target_mips64
#define semihosting_get_arg semihosting_get_arg_mips64
#define semihosting_get_argc semihosting_get_argc_mips64

1
qemu/mips64el.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_mips64el
#define scr_write scr_write_mips64el
#define sctlr_write sctlr_write_mips64el
#define semihosting_enabled semihosting_enabled_mips64el
#define semihosting_get_target semihosting_get_target_mips64el
#define semihosting_get_arg semihosting_get_arg_mips64el
#define semihosting_get_argc semihosting_get_argc_mips64el

1
qemu/mipsel.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_mipsel
#define scr_write scr_write_mipsel
#define sctlr_write sctlr_write_mipsel
#define semihosting_enabled semihosting_enabled_mipsel
#define semihosting_get_target semihosting_get_target_mipsel
#define semihosting_get_arg semihosting_get_arg_mipsel
#define semihosting_get_argc semihosting_get_argc_mipsel

1
qemu/powerpc.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_powerpc
#define scr_write scr_write_powerpc
#define sctlr_write sctlr_write_powerpc
#define semihosting_enabled semihosting_enabled_powerpc
#define semihosting_get_target semihosting_get_target_powerpc
#define semihosting_get_arg semihosting_get_arg_powerpc
#define semihosting_get_argc semihosting_get_argc_powerpc

1
qemu/sparc.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_sparc
#define scr_write scr_write_sparc
#define sctlr_write sctlr_write_sparc
#define semihosting_enabled semihosting_enabled_sparc
#define semihosting_get_target semihosting_get_target_sparc
#define semihosting_get_arg semihosting_get_arg_sparc
#define semihosting_get_argc semihosting_get_argc_sparc

1
qemu/sparc64.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_sparc64
#define scr_write scr_write_sparc64
#define sctlr_write sctlr_write_sparc64
#define semihosting_enabled semihosting_enabled_sparc64
#define semihosting_get_target semihosting_get_target_sparc64
#define semihosting_get_arg semihosting_get_arg_sparc64
#define semihosting_get_argc semihosting_get_argc_sparc64

1
qemu/target-arm/cpu.h
View file

@ -58,6 +58,7 @@
#define EXCP_SMC 13 /* Secure Monitor Call */
#define EXCP_VIRQ 14
#define EXCP_VFIQ 15
#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2

7
qemu/target-arm/helper-a64.c
View file

@ -570,6 +570,13 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
case EXCP_VFIQ:
addr += 0x100;
break;
case EXCP_SEMIHOST:
/* UNICORN: Commented out
qemu_log_mask(CPU_LOG_INT,
"...handling as semihosting call 0x%" PRIx64 "\n",
env->xregs[0]);
env->xregs[0] = do_arm_semihosting(env);*/
return;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}

2
qemu/target-arm/internals.h
View file

@ -36,6 +36,7 @@ static inline bool excp_is_internal(int excp)
|| excp == EXCP_HALTED
|| excp == EXCP_EXCEPTION_EXIT
|| excp == EXCP_KERNEL_TRAP
|| excp == EXCP_SEMIHOST
|| excp == EXCP_STREX;
}
@ -59,6 +60,7 @@ static const char * const excnames[] = {
"Secure Monitor Call",
"Virtual IRQ",
"Virtual FIQ",
"Semihosting call",
};
static inline void arm_log_exception(int idx)

23
qemu/target-arm/translate-a64.c
View file

@ -1584,8 +1584,27 @@ static void disas_exc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
break;
}
/* HLT */
unsupported_encoding(s, insn);
/* HLT. This has two purposes.
* Architecturally, it is an external halting debug instruction.
* Since QEMU doesn't implement external debug, we treat this as
* it is required for halting debug disabled: it will UNDEF.
* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
*/
if (semihosting_enabled() && imm16 == 0xf000) {
#ifndef CONFIG_USER_ONLY
/* In system mode, don't allow userspace access to semihosting,
* to provide some semblance of security (and for consistency
* with our 32-bit semihosting).
*/
if (s->current_el == 0) {
unsupported_encoding(s, insn);
break;
}
#endif
gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
} else {
unsupported_encoding(s, insn);
}
break;
case 5:
if (op2_ll < 1 || op2_ll > 3) {

1
qemu/x86_64.h
View file

@ -2582,7 +2582,6 @@
#define save_globals save_globals_x86_64
#define scr_write scr_write_x86_64
#define sctlr_write sctlr_write_x86_64
#define semihosting_enabled semihosting_enabled_x86_64
#define semihosting_get_target semihosting_get_target_x86_64
#define semihosting_get_arg semihosting_get_arg_x86_64
#define semihosting_get_argc semihosting_get_argc_x86_64