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target/arm: Tidy SVE tszimm shift formats

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Rather than require the user to fill in the immediate (shl or shr),
create full formats that include the immediate.
This commit is contained in:
Richard Henderson 2021-02-26 14:35:49 -05:00 committed by Lioncash
parent da41a23a1b
commit 1bedcfbda3
1 changed files with 16 additions and 19 deletions
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35
qemu/target/arm/sve.decode
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@ -150,13 +150,17 @@
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
# Two register operand, one immediate operand, with predicate,
# element size encoded as TSZHL. User must fill in imm.
@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
&rpri_esz rn=%reg_movprfx esz=%tszimm_esz
# element size encoded as TSZHL.
@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
&rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
&rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
# Similarly without predicate.
@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
&rri_esz esz=%tszimm16_esz
@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
&rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
&rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
# Two register operand, one immediate operand, with 4-bit predicate.
# User must fill in imm.
@ -289,14 +293,10 @@ UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
### SVE Shift by Immediate - Predicated Group
# SVE bitwise shift by immediate (predicated)
ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shl
ASRD 00000100 .. 000 100 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
# SVE bitwise shift by vector (predicated)
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
@ -400,12 +400,9 @@ RDVL 00000100 101 11111 01010 imm:s6 rd:5
### SVE Bitwise Shift - Unpredicated Group
# SVE bitwise shift by immediate (unpredicated)
ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
@rd_rn_tszimm imm=%tszimm16_shr
LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
@rd_rn_tszimm imm=%tszimm16_shr
LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
@rd_rn_tszimm imm=%tszimm16_shl
ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
# SVE bitwise shift by wide elements (unpredicated)
# Note esz != 3