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target/mips: optimize WSBH, DSBH and DSHD

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Use the same mask to avoid having to load two different constants.

Backports commit 06a57e5cc7ee5292a4915117ebf951e310a28264 from qemu
This commit is contained in:
Aurelien Jarno 2018-03-03 22:47:30 -05:00 committed by Lioncash
parent 342fa7135d
commit 1c0169842d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 6 deletions
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18
qemu/target/mips/translate.c
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@ -4635,12 +4635,14 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_WSBH: case OPC_WSBH:
{ {
TCGv t1 = tcg_temp_new(tcg_ctx); TCGv t1 = tcg_temp_new(tcg_ctx);
TCGv t2 = tcg_const_tl(tcg_ctx, 0x00FF00FF);
tcg_gen_shri_tl(tcg_ctx, t1, t0, 8); tcg_gen_shri_tl(tcg_ctx, t1, t0, 8);
tcg_gen_andi_tl(tcg_ctx, t1, t1, 0x00FF00FF); tcg_gen_and_tl(tcg_ctx, t1, t1, t2);
tcg_gen_and_tl(tcg_ctx, t0, t0, t2);
tcg_gen_shli_tl(tcg_ctx, t0, t0, 8); tcg_gen_shli_tl(tcg_ctx, t0, t0, 8);
tcg_gen_andi_tl(tcg_ctx, t0, t0, ~0x00FF00FF);
tcg_gen_or_tl(tcg_ctx, t0, t0, t1); tcg_gen_or_tl(tcg_ctx, t0, t0, t1);
tcg_temp_free(tcg_ctx, t2);
tcg_temp_free(tcg_ctx, t1); tcg_temp_free(tcg_ctx, t1);
tcg_gen_ext32s_tl(tcg_ctx, cpu_gpr[rd], t0); tcg_gen_ext32s_tl(tcg_ctx, cpu_gpr[rd], t0);
} }
@ -4655,27 +4657,31 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSBH: case OPC_DSBH:
{ {
TCGv t1 = tcg_temp_new(tcg_ctx); TCGv t1 = tcg_temp_new(tcg_ctx);
TCGv t2 = tcg_const_tl(tcg_ctx, 0x00FF00FF00FF00FFULL);
tcg_gen_shri_tl(tcg_ctx, t1, t0, 8); tcg_gen_shri_tl(tcg_ctx, t1, t0, 8);
tcg_gen_andi_tl(tcg_ctx, t1, t1, 0x00FF00FF00FF00FFULL); tcg_gen_and_tl(tcg_ctx, t1, t1, t2);
tcg_gen_and_tl(tcg_ctx, t0, t0, t2);
tcg_gen_shli_tl(tcg_ctx, t0, t0, 8); tcg_gen_shli_tl(tcg_ctx, t0, t0, 8);
tcg_gen_andi_tl(tcg_ctx, t0, t0, ~0x00FF00FF00FF00FFULL);
tcg_gen_or_tl(tcg_ctx, cpu_gpr[rd], t0, t1); tcg_gen_or_tl(tcg_ctx, cpu_gpr[rd], t0, t1);
tcg_temp_free(tcg_ctx, t2);
tcg_temp_free(tcg_ctx, t1); tcg_temp_free(tcg_ctx, t1);
} }
break; break;
case OPC_DSHD: case OPC_DSHD:
{ {
TCGv t1 = tcg_temp_new(tcg_ctx); TCGv t1 = tcg_temp_new(tcg_ctx);
TCGv t2 = tcg_const_tl(tcg_ctx, 0x0000FFFF0000FFFFULL);
tcg_gen_shri_tl(tcg_ctx, t1, t0, 16); tcg_gen_shri_tl(tcg_ctx, t1, t0, 16);
tcg_gen_andi_tl(tcg_ctx, t1, t1, 0x0000FFFF0000FFFFULL); tcg_gen_and_tl(tcg_ctx, t1, t1, t2);
tcg_gen_and_tl(tcg_ctx, t0, t0, t2);
tcg_gen_shli_tl(tcg_ctx, t0, t0, 16); tcg_gen_shli_tl(tcg_ctx, t0, t0, 16);
tcg_gen_andi_tl(tcg_ctx, t0, t0, ~0x0000FFFF0000FFFFULL);
tcg_gen_or_tl(tcg_ctx, t0, t0, t1); tcg_gen_or_tl(tcg_ctx, t0, t0, t1);
tcg_gen_shri_tl(tcg_ctx, t1, t0, 32); tcg_gen_shri_tl(tcg_ctx, t1, t0, 32);
tcg_gen_shli_tl(tcg_ctx, t0, t0, 32); tcg_gen_shli_tl(tcg_ctx, t0, t0, 32);
tcg_gen_or_tl(tcg_ctx, cpu_gpr[rd], t0, t1); tcg_gen_or_tl(tcg_ctx, cpu_gpr[rd], t0, t1);
tcg_temp_free(tcg_ctx, t2);
tcg_temp_free(tcg_ctx, t1); tcg_temp_free(tcg_ctx, t1);
} }
break; break;