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atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32
ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for all MIPS host builds, including those using the n32 ABI. n32 is the MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU for an n32 host with support for a 64b target architecture then TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various atomic_* functions to generate errors. Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we already do for x86_64/x32. Backports commit c5b00c1684f3317e887c7401b58dde54c2b05354 from qemu
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@ -107,9 +107,10 @@ void _ReadWriteBarrier(void);
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* those few cases by hand.
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*
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* Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
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* Sparc we always force the use of sparcv9 in configure.
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* Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
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* n64 (LP64) ABIs are both detected using __mips64.
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*/
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#if defined(__x86_64__) || defined(__sparc__)
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#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
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# define ATOMIC_REG_SIZE 8
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#else
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# define ATOMIC_REG_SIZE sizeof(void *)
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