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target/arm: Implement VFP fp16 VSEL
Implement the fp16 versions of the VFP VSEL instruction. Backports commit 11e78fecdf2d605cfed33aa09bbcf0cc4fb95886
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parent
beee4ad7f3
commit
1c8088b48a
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@ -193,19 +193,22 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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{
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t rd, rn, rm;
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uint32_t rd, rn, rm;
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bool dp = a->dp;
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int sz = a->sz;
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if (!dc_isar_feature(aa32_vsel, s)) {
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if (!dc_isar_feature(aa32_vsel, s)) {
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return false;
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return false;
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}
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (sz == 3 && !dc_isar_feature(aa32_fpdp_v2, s)) {
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if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
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return false;
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}
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if (sz == 1 && !dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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return false;
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}
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
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if (sz == 3 && !dc_isar_feature(aa32_simd_r32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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((a->vm | a->vn | a->vd) & 0x10)) {
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return false;
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return false;
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}
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}
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@ -218,7 +221,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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return true;
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return true;
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}
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}
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if (dp) {
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if (sz == 3) {
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TCGv_i64 frn, frm, dest;
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TCGv_i64 frn, frm, dest;
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TCGv_i64 tmp, zero, zf, nf, vf;
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TCGv_i64 tmp, zero, zf, nf, vf;
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@ -311,6 +314,10 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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tcg_temp_free_i32(tcg_ctx, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp);
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break;
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break;
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}
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}
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/* For fp16 the top half is always zeroes */
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if (sz == 1) {
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tcg_gen_andi_i32(tcg_ctx, dest, dest, 0xffff);
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}
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neon_store_reg32(s, dest, rd);
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neon_store_reg32(s, dest, rd);
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tcg_temp_free_i32(tcg_ctx, frn);
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tcg_temp_free_i32(tcg_ctx, frn);
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tcg_temp_free_i32(tcg_ctx, frm);
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tcg_temp_free_i32(tcg_ctx, frm);
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@ -44,10 +44,12 @@
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@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
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@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
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@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
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VSEL 1111 1110 0. cc:2 .... .... 1001 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=1
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VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
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VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
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vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=2
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VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
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VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
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vm=%vm_dp vn=%vn_dp vd=%vd_dp sz=3
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VMAXNM_hp 1111 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s
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VMAXNM_hp 1111 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s
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VMINNM_hp 1111 1110 1.00 .... .... 1001 .1.0 .... @vfp_dnm_s
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VMINNM_hp 1111 1110 1.00 .... .... 1001 .1.0 .... @vfp_dnm_s
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