yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-02-02 06:41:03 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Convert Neon VPMAX/VPMIN 3-reg-same insns to decodetree

Browse source 
Convert the Neon integer VPMAX and VPMIN 3-reg-same insns to
decodetree. These are 'pairwise' operations.

Backports commit 059c2398a2b1ae86c6722c45e79fb0d0f4d95b1d from qemu
This commit is contained in:
Peter Maydell 2020-05-15 22:57:54 -04:00 committed by Lioncash
parent f35ae14ab4
commit 1cc6451cb6
3 changed files with 83 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
qemu/target/arm/neon-dp.decode
View file

@ -42,6 +42,9 @@
@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
@ -143,6 +146,12 @@ VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
VPMAX_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \

72
qemu/target/arm/translate-neon.inc.c
View file

@ -941,3 +941,75 @@ DO_3SAME_32_ENV(VQSHL_S, qshl_s)
DO_3SAME_32_ENV(VQSHL_U, qshl_u)
DO_3SAME_32_ENV(VQRSHL_S, qrshl_s)
DO_3SAME_32_ENV(VQRSHL_U, qrshl_u)
static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
{
/* Operations handled pairwise 32 bits at a time */
TCGv_i32 tmp, tmp2, tmp3;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
if (a->size == 3) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
assert(a->q == 0); /* enforced by decode patterns */
/*
* Note that we have to be careful not to clobber the source operands
* in the "vm == vd" case by storing the result of the first pass too
* early. Since Q is 0 there are always just two passes, so instead
* of a complicated loop over each pass we just unroll.
*/
tmp = neon_load_reg(s, a->vn, 0);
tmp2 = neon_load_reg(s, a->vn, 1);
fn(tcg_ctx, tmp, tmp, tmp2);
tcg_temp_free_i32(tcg_ctx, tmp2);
tmp3 = neon_load_reg(s, a->vm, 0);
tmp2 = neon_load_reg(s, a->vm, 1);
fn(tcg_ctx, tmp3, tmp3, tmp2);
tcg_temp_free_i32(tcg_ctx, tmp2);
neon_store_reg(s, a->vd, 0, tmp);
neon_store_reg(s, a->vd, 1, tmp3);
return true;
}
#define DO_3SAME_PAIR(INSN, func) \
static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
{ \
static NeonGenTwoOpFn * const fns[] = { \
gen_helper_neon_##func##8, \
gen_helper_neon_##func##16, \
gen_helper_neon_##func##32, \
}; \
if (a->size > 2) { \
return false; \
} \
return do_3same_pair(s, a, fns[a->size]); \
}
/* 32-bit pairwise ops end up the same as the elementwise versions. */
#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32
#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
DO_3SAME_PAIR(VPMAX_S, pmax_s)
DO_3SAME_PAIR(VPMIN_S, pmin_s)
DO_3SAME_PAIR(VPMAX_U, pmax_u)
DO_3SAME_PAIR(VPMIN_U, pmin_u)

16
qemu/target/arm/translate.c
View file

@ -3122,12 +3122,6 @@ static inline void gen_neon_rsb(DisasContext *s, int size, TCGv_i32 t0, TCGv_i32
}
}
/* 32-bit pairwise ops end up the same as the elementwise versions. */
#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32
#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
#define GEN_NEON_INTEGER_OP_ENV(name) do { \
switch ((size << 1) | u) { \
case 0: \
@ -5569,6 +5563,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VQSHL:
case NEON_3R_VRSHL:
case NEON_3R_VQRSHL:
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
/* Already handled by decodetree */
return 1;
}
@ -5580,8 +5576,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
pairwise = 0;
switch (op) {
case NEON_3R_VPADD_VQRDMLAH:
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
pairwise = 1;
break;
case NEON_3R_FLOAT_ARITH:
@ -5638,12 +5632,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(s, rm, pass);
}
switch (op) {
case NEON_3R_VPMAX:
GEN_NEON_INTEGER_OP(pmax);
break;
case NEON_3R_VPMIN:
GEN_NEON_INTEGER_OP(pmin);
break;
case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
if (!u) { /* VQDMULH */
switch (size) {