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target/riscv: Only flush TLB if SATP.ASID changes

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There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Backports commit 1e0d985fa9136a563168a3da66f3d17820404ee2 from qemu
This commit is contained in:
Jonathan Behrens 2019-05-28 19:22:49 -04:00 committed by Lioncash
parent 7922aa54c0
commit 1d6acaa604
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 1 deletions
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4
qemu/target/riscv/csr.c
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@ -734,7 +734,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
tlb_flush(CPU(riscv_env_get_cpu(env)));
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
}
env->satp = val;
}
}