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target-sparc: Store %asi in TB flags
Knowing the value of %asi at translation time means that we can handle the common settings without a function call. The steady state appears to be %asi == ASI_P, so that sparcv9 code can use offset forms of lda/sta. The %asi register gets pushed and popped on entry to certain functions, but it rarely takes on values other than ASI_P or ASI_AIUP. Therefore we're unlikely to be expanding the set of TBs created. Backports commit a6d567e523ed7e928861f3caa5d49368af3f330d from qemu
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080281bc9c
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1dcd14d434
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@ -727,6 +727,7 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
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#define TB_FLAG_MMU_MASK 7
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#define TB_FLAG_MMU_MASK 7
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#define TB_FLAG_FPU_ENABLED (1 << 4)
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#define TB_FLAG_FPU_ENABLED (1 << 4)
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#define TB_FLAG_AM_ENABLED (1 << 5)
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#define TB_FLAG_AM_ENABLED (1 << 5)
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#define TB_FLAG_ASI_SHIFT 24
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static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
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static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *pflags)
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target_ulong *cs_base, uint32_t *pflags)
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@ -744,6 +745,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
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&& (env->fprs & FPRS_FEF)) {
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&& (env->fprs & FPRS_FEF)) {
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flags |= TB_FLAG_FPU_ENABLED;
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flags |= TB_FLAG_FPU_ENABLED;
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}
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}
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flags |= env->asi << TB_FLAG_ASI_SHIFT;
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#else
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#else
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if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
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if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
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flags |= TB_FLAG_FPU_ENABLED;
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flags |= TB_FLAG_FPU_ENABLED;
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@ -50,6 +50,9 @@ typedef struct DisasContext {
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TCGv ttl[5];
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TCGv ttl[5];
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int n_t32;
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int n_t32;
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int n_ttl;
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int n_ttl;
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#ifdef TARGET_SPARC64
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int asi;
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#endif
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// Unicorn engine
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// Unicorn engine
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struct uc_struct *uc;
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struct uc_struct *uc;
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@ -2100,20 +2103,19 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
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static TCGv_i32 gen_get_asi(DisasContext *dc, int insn)
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static TCGv_i32 gen_get_asi(DisasContext *dc, int insn)
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{
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{
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TCGContext *tcg_ctx = dc->uc->tcg_ctx;
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TCGContext *tcg_ctx = dc->uc->tcg_ctx;
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TCGv_i32 r_asi = tcg_temp_new_i32(tcg_ctx);
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int asi;
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if (IS_IMM) {
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if (IS_IMM) {
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r_asi = tcg_temp_new_i32(tcg_ctx);
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#ifdef TARGET_SPARC64
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#ifdef TARGET_SPARC64
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tcg_gen_mov_i32(tcg_ctx, r_asi, tcg_ctx->cpu_asi);
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asi = dc->asi;
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#else
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#else
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gen_exception(dc, TT_ILL_INSN);
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gen_exception(dc, TT_ILL_INSN);
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tcg_gen_movi_i32(tcg_ctx, r_asi, 0);
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asi = 0;
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#endif
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#endif
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} else {
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} else {
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tcg_gen_movi_i32(tcg_ctx, r_asi, GET_FIELD(insn, 19, 26));
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asi = GET_FIELD(insn, 19, 26);
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}
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}
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return r_asi;
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return tcg_const_i32(tcg_ctx, asi);
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}
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}
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static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
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static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
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@ -2840,7 +2842,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
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gen_store_gpr(dc, rd, cpu_dst);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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break;
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case 0x3: /* V9 rdasi */
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case 0x3: /* V9 rdasi */
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tcg_gen_ext_i32_tl(tcg_ctx, cpu_dst, tcg_ctx->cpu_asi);
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tcg_gen_movi_tl(tcg_ctx, cpu_dst, dc->asi);
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gen_store_gpr(dc, rd, cpu_dst);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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break;
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case 0x4: /* V9 rdtick */
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case 0x4: /* V9 rdtick */
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@ -3744,7 +3746,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
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/* undefined in the SPARCv8 manual, nop on the microSPARC II */
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/* undefined in the SPARCv8 manual, nop on the microSPARC II */
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case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
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case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
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case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
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case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
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/* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */
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/* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */
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case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
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case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
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case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
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case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
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@ -3765,7 +3767,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
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case 0x3: /* V9 wrasi */
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case 0x3: /* V9 wrasi */
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tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
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tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
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tcg_gen_andi_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, 0xff);
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tcg_gen_andi_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, 0xff);
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tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_asi, cpu_tmp0);
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tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
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offsetof(CPUSPARCState, asi));
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/* End TB to notice changed ASI. */
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save_state(dc);
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gen_op_next_insn(dc);
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tcg_gen_exit_tb(tcg_ctx, 0);
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dc->is_br = 1;
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break;
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break;
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case 0x6: /* V9 wrfprs */
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case 0x6: /* V9 wrfprs */
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tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
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tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
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@ -5349,6 +5357,9 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
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dc->fpu_enabled = tb_fpu_enabled(tb->flags);
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dc->fpu_enabled = tb_fpu_enabled(tb->flags);
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dc->address_mask_32bit = tb_am_enabled(tb->flags);
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dc->address_mask_32bit = tb_am_enabled(tb->flags);
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dc->singlestep = (cs->singlestep_enabled); // || singlestep);
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dc->singlestep = (cs->singlestep_enabled); // || singlestep);
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#ifdef TARGET_SPARC64
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dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
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#endif
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// early check to see if the address of this block is the until address
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// early check to see if the address of this block is the until address
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if (pc_start == env->uc->addr_end) {
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if (pc_start == env->uc->addr_end) {
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@ -5500,8 +5511,6 @@ void gen_intermediate_code_init(CPUSPARCState *env)
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#ifdef TARGET_SPARC64
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#ifdef TARGET_SPARC64
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tcg_ctx->cpu_xcc = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, xcc),
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tcg_ctx->cpu_xcc = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, xcc),
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"xcc");
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"xcc");
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tcg_ctx->cpu_asi = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, asi),
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"asi");
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tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fprs),
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tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fprs),
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"fprs");
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"fprs");
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@ -923,7 +923,7 @@ struct TCGContext {
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/* global register indexes */
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/* global register indexes */
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TCGv_ptr cpu_regwptr;
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TCGv_ptr cpu_regwptr;
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TCGv_i32 cpu_psr;
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TCGv_i32 cpu_psr;
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TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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TCGv_i32 cpu_xcc, cpu_fprs;
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/* Floating point registers */
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/* Floating point registers */
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TCGv_i64 cpu_fpr[32]; // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc
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TCGv_i64 cpu_fpr[32]; // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc
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