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target-sparc: Store %asi in TB flags

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Knowing the value of %asi at translation time means that we
can handle the common settings without a function call.

The steady state appears to be %asi == ASI_P, so that sparcv9
code can use offset forms of lda/sta. The %asi register gets
pushed and popped on entry to certain functions, but it rarely
takes on values other than ASI_P or ASI_AIUP. Therefore we're
unlikely to be expanding the set of TBs created.

Backports commit a6d567e523ed7e928861f3caa5d49368af3f330d from qemu
This commit is contained in:
Richard Henderson 2018-02-25 05:15:30 -05:00 committed by Lioncash
parent 080281bc9c
commit 1dcd14d434
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 23 additions and 12 deletions
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2
qemu/target-sparc/cpu.h
View file

@ -727,6 +727,7 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_MMU_MASK 7 #define TB_FLAG_MMU_MASK 7
#define TB_FLAG_FPU_ENABLED (1 << 4) #define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5) #define TB_FLAG_AM_ENABLED (1 << 5)
#define TB_FLAG_ASI_SHIFT 24
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags) target_ulong *cs_base, uint32_t *pflags)
@ -744,6 +745,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
&& (env->fprs & FPRS_FEF)) { && (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED; flags |= TB_FLAG_FPU_ENABLED;
} }
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else #else
if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) { if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
flags |= TB_FLAG_FPU_ENABLED; flags |= TB_FLAG_FPU_ENABLED;

31
qemu/target-sparc/translate.c
View file

@ -50,6 +50,9 @@ typedef struct DisasContext {
TCGv ttl[5]; TCGv ttl[5];
int n_t32; int n_t32;
int n_ttl; int n_ttl;
#ifdef TARGET_SPARC64
int asi;
#endif
// Unicorn engine // Unicorn engine
struct uc_struct *uc; struct uc_struct *uc;
@ -2100,20 +2103,19 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
static TCGv_i32 gen_get_asi(DisasContext *dc, int insn) static TCGv_i32 gen_get_asi(DisasContext *dc, int insn)
{ {
TCGContext *tcg_ctx = dc->uc->tcg_ctx; TCGContext *tcg_ctx = dc->uc->tcg_ctx;
TCGv_i32 r_asi = tcg_temp_new_i32(tcg_ctx); int asi;
if (IS_IMM) { if (IS_IMM) {
r_asi = tcg_temp_new_i32(tcg_ctx);
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
tcg_gen_mov_i32(tcg_ctx, r_asi, tcg_ctx->cpu_asi); asi = dc->asi;
#else #else
gen_exception(dc, TT_ILL_INSN); gen_exception(dc, TT_ILL_INSN);
tcg_gen_movi_i32(tcg_ctx, r_asi, 0); asi = 0;
#endif #endif
} else { } else {
tcg_gen_movi_i32(tcg_ctx, r_asi, GET_FIELD(insn, 19, 26)); asi = GET_FIELD(insn, 19, 26);
} }
return r_asi; return tcg_const_i32(tcg_ctx, asi);
} }
static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
@ -2840,7 +2842,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
gen_store_gpr(dc, rd, cpu_dst); gen_store_gpr(dc, rd, cpu_dst);
break; break;
case 0x3: /* V9 rdasi */ case 0x3: /* V9 rdasi */
tcg_gen_ext_i32_tl(tcg_ctx, cpu_dst, tcg_ctx->cpu_asi); tcg_gen_movi_tl(tcg_ctx, cpu_dst, dc->asi);
gen_store_gpr(dc, rd, cpu_dst); gen_store_gpr(dc, rd, cpu_dst);
break; break;
case 0x4: /* V9 rdtick */ case 0x4: /* V9 rdtick */
@ -3744,7 +3746,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
/* undefined in the SPARCv8 manual, nop on the microSPARC II */ /* undefined in the SPARCv8 manual, nop on the microSPARC II */
case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
/* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */ /* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
@ -3765,7 +3767,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
case 0x3: /* V9 wrasi */ case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
tcg_gen_andi_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, 0xff); tcg_gen_andi_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, 0xff);
tcg_gen_trunc_tl_i32(tcg_ctx, tcg_ctx->cpu_asi, cpu_tmp0); tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
offsetof(CPUSPARCState, asi));
/* End TB to notice changed ASI. */
save_state(dc);
gen_op_next_insn(dc);
tcg_gen_exit_tb(tcg_ctx, 0);
dc->is_br = 1;
break; break;
case 0x6: /* V9 wrfprs */ case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
@ -5349,6 +5357,9 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (cs->singlestep_enabled); // || singlestep); dc->singlestep = (cs->singlestep_enabled); // || singlestep);
#ifdef TARGET_SPARC64
dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
#endif
// early check to see if the address of this block is the until address // early check to see if the address of this block is the until address
if (pc_start == env->uc->addr_end) { if (pc_start == env->uc->addr_end) {
@ -5500,8 +5511,6 @@ void gen_intermediate_code_init(CPUSPARCState *env)
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
tcg_ctx->cpu_xcc = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, xcc), tcg_ctx->cpu_xcc = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, xcc),
"xcc"); "xcc");
tcg_ctx->cpu_asi = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, asi),
"asi");
tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fprs), tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fprs),
"fprs"); "fprs");

2
qemu/tcg/tcg.h
View file

@ -923,7 +923,7 @@ struct TCGContext {
/* global register indexes */ /* global register indexes */
TCGv_ptr cpu_regwptr; TCGv_ptr cpu_regwptr;
TCGv_i32 cpu_psr; TCGv_i32 cpu_psr;
TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs; TCGv_i32 cpu_xcc, cpu_fprs;
/* Floating point registers */ /* Floating point registers */
TCGv_i64 cpu_fpr[32]; // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc TCGv_i64 cpu_fpr[32]; // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc