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target/arm: Add support for cortex-m7 CPU

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This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.

Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".

Backports commit cf7beda5072e106ddce875c1996446540c5fe239 from qemu
This commit is contained in:
Christophe Lyon 2020-01-07 17:52:12 -05:00 committed by Lioncash
parent 4fdf05f89e
commit 1df67780cd
1 changed files with 34 additions and 0 deletions
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34
qemu/target/arm/cpu.c
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@ -1236,6 +1236,38 @@ static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->isar.id_isar6 = 0x00000000; cpu->isar.id_isar6 = 0x00000000;
} }
static void cortex_m7_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{
ARMCPU *cpu = ARM_CPU(uc, obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x411fc272; /* r1p2 */
cpu->pmsav7_dregion = 8;
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12000011;
cpu->isar.mvfr2 = 0x00000040;
cpu->id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200;
cpu->id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x00100030;
cpu->id_mmfr1 = 0x00000000;
cpu->id_mmfr2 = 0x01000000;
cpu->id_mmfr3 = 0x00000000;
cpu->isar.id_isar0 = 0x01101110;
cpu->isar.id_isar1 = 0x02112000;
cpu->isar.id_isar2 = 0x20232231;
cpu->isar.id_isar3 = 0x01111131;
cpu->isar.id_isar4 = 0x01310132;
cpu->isar.id_isar5 = 0x00000000;
cpu->isar.id_isar6 = 0x00000000;
}
static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque) static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{ {
ARMCPU *cpu = ARM_CPU(uc, obj); ARMCPU *cpu = ARM_CPU(uc, obj);
@ -1811,6 +1843,8 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init }, .class_init = arm_v7m_class_init },
{ .name = "cortex-m4", .initfn = cortex_m4_initfn, { .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init }, .class_init = arm_v7m_class_init },
{ .name = "cortex-m7", .initfn = cortex_m7_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn, { .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init }, .class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn }, { .name = "cortex-r5", .initfn = cortex_r5_initfn },