yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-09 10:35:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Implement ARMv8.4-CondM

Browse source 
Backports commit b89d9c988a988d5547c73e2bc43f59b0c07420a5 from qemu
This commit is contained in:
Richard Henderson 2019-03-05 22:59:45 -05:00 committed by Lioncash
parent 65a3f3be5b
commit 1dfa15a683
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 106 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
qemu/target/arm/cpu.h
View file

@ -3411,6 +3411,11 @@ static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
}
static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
}
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;

1
qemu/target/arm/cpu64.c
View file

@ -254,6 +254,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
cpu->isar.id_aa64isar0 = t;
t = cpu->isar.id_aa64isar1;

101
qemu/target/arm/translate-a64.c
View file

@ -1733,6 +1733,14 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
s->base.is_jmp = DISAS_TOO_MANY;
switch (op) {
case 0x00: /* CFINV */
if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
goto do_unallocated;
}
tcg_gen_xori_i32(tcg_ctx, tcg_ctx->cpu_CF, tcg_ctx->cpu_CF, 1);
s->base.is_jmp = DISAS_NEXT;
break;
case 0x05: /* SPSel */
if (s->current_el == 0) {
goto do_unallocated;
@ -1786,7 +1794,6 @@ static void gen_get_nzcv(TCGContext *tcg_ctx, TCGv_i64 tcg_rt)
}
static void gen_set_nzcv(TCGContext *tcg_ctx, TCGv_i64 tcg_rt)
{
TCGv_i32 nzcv = tcg_temp_new_i32(tcg_ctx);
@ -4613,6 +4620,86 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
}
}
/*
* Rotate right into flags
* 31 30 29 21 15 10 5 4 0
* +--+--+--+-----------------+--------+-----------+------+--+------+
* |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
* +--+--+--+-----------------+--------+-----------+------+--+------+
*/
static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int mask = extract32(insn, 0, 4);
int o2 = extract32(insn, 4, 1);
int rn = extract32(insn, 5, 5);
int imm6 = extract32(insn, 15, 6);
int sf_op_s = extract32(insn, 29, 3);
TCGv_i64 tcg_rn;
TCGv_i32 nzcv;
if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) {
unallocated_encoding(s);
return;
}
tcg_rn = read_cpu_reg(s, rn, 1);
tcg_gen_rotri_i64(tcg_ctx, tcg_rn, tcg_rn, imm6);
nzcv = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, nzcv, tcg_rn);
if (mask & 8) { /* N */
tcg_gen_shli_i32(tcg_ctx, tcg_ctx->cpu_NF, nzcv, 31 - 3);
}
if (mask & 4) { /* Z */
tcg_gen_not_i32(tcg_ctx, tcg_ctx->cpu_ZF, nzcv);
tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, 4);
}
if (mask & 2) { /* C */
tcg_gen_extract_i32(tcg_ctx, tcg_ctx->cpu_CF, nzcv, 1, 1);
}
if (mask & 1) { /* V */
tcg_gen_shli_i32(tcg_ctx, tcg_ctx->cpu_VF, nzcv, 31 - 0);
}
tcg_temp_free_i32(tcg_ctx, nzcv);
}
/*
* Evaluate into flags
* 31 30 29 21 15 14 10 5 4 0
* +--+--+--+-----------------+---------+----+---------+------+--+------+
* |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
* +--+--+--+-----------------+---------+----+---------+------+--+------+
*/
static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int o3_mask = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int o2 = extract32(insn, 15, 6);
int sz = extract32(insn, 14, 1);
int sf_op_s = extract32(insn, 29, 3);
TCGv_i32 tmp;
int shift;
if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||
!dc_isar_feature(aa64_condm_4, s)) {
unallocated_encoding(s);
return;
}
shift = sz ? 16 : 24; /* SETF16 or SETF8 */
tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, cpu_reg(s, rn));
tcg_gen_shli_i32(tcg_ctx, tcg_ctx->cpu_NF, tmp, shift);
tcg_gen_shli_i32(tcg_ctx, tcg_ctx->cpu_VF, tmp, shift - 1);
tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF);
tcg_gen_xor_i32(tcg_ctx, tcg_ctx->cpu_VF, tcg_ctx->cpu_VF, tcg_ctx->cpu_NF);
tcg_temp_free_i32(tcg_ctx, tmp);
}
/* Conditional compare (immediate / register)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
@ -5294,6 +5381,18 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
disas_adc_sbc(s, insn);
break;
case 0x01: /* Rotate right into flags */
case 0x21:
disas_rotate_right_into_flags(s, insn);
break;
case 0x02: /* Evaluate into flags */
case 0x12:
case 0x22:
case 0x32:
disas_evaluate_into_flags(s, insn);
break;
default:
goto do_unallocated;
}